43 open Hints_declaration
79 type identifier = PreIdentifiers.identifier
82 PreIdentifiers.identifierTag -> PreIdentifiers.identifier -> identifier **)
86 type addressing_mode =
87 | DIRECT of BitVector.byte
88 | INDIRECT of BitVector.bit
89 | EXT_INDIRECT of BitVector.bit
90 | REGISTER of BitVector.bitVector
94 | DATA of BitVector.byte
95 | DATA16 of BitVector.word
101 | BIT_ADDR of BitVector.byte
102 | N_BIT_ADDR of BitVector.byte
103 | RELATIVE of BitVector.byte
104 | ADDR11 of BitVector.word11
105 | ADDR16 of BitVector.word
107 (** val addressing_mode_rect_Type4 :
108 (BitVector.byte -> 'a1) -> (BitVector.bit -> 'a1) -> (BitVector.bit ->
109 'a1) -> (BitVector.bitVector -> 'a1) -> 'a1 -> 'a1 -> 'a1 ->
110 (BitVector.byte -> 'a1) -> (BitVector.word -> 'a1) -> 'a1 -> 'a1 -> 'a1
111 -> 'a1 -> 'a1 -> (BitVector.byte -> 'a1) -> (BitVector.byte -> 'a1) ->
112 (BitVector.byte -> 'a1) -> (BitVector.word11 -> 'a1) -> (BitVector.word
113 -> 'a1) -> addressing_mode -> 'a1 **)
114 let rec addressing_mode_rect_Type4 h_DIRECT h_INDIRECT h_EXT_INDIRECT h_REGISTER h_ACC_A h_ACC_B h_DPTR h_DATA h_DATA16 h_ACC_DPTR h_ACC_PC h_EXT_INDIRECT_DPTR h_INDIRECT_DPTR h_CARRY h_BIT_ADDR h_N_BIT_ADDR h_RELATIVE h_ADDR11 h_ADDR16 = function
115 | DIRECT x_33 -> h_DIRECT x_33
116 | INDIRECT x_34 -> h_INDIRECT x_34
117 | EXT_INDIRECT x_35 -> h_EXT_INDIRECT x_35
118 | REGISTER x_36 -> h_REGISTER x_36
122 | DATA x_37 -> h_DATA x_37
123 | DATA16 x_38 -> h_DATA16 x_38
124 | ACC_DPTR -> h_ACC_DPTR
126 | EXT_INDIRECT_DPTR -> h_EXT_INDIRECT_DPTR
127 | INDIRECT_DPTR -> h_INDIRECT_DPTR
129 | BIT_ADDR x_39 -> h_BIT_ADDR x_39
130 | N_BIT_ADDR x_40 -> h_N_BIT_ADDR x_40
131 | RELATIVE x_41 -> h_RELATIVE x_41
132 | ADDR11 x_42 -> h_ADDR11 x_42
133 | ADDR16 x_43 -> h_ADDR16 x_43
135 (** val addressing_mode_rect_Type5 :
136 (BitVector.byte -> 'a1) -> (BitVector.bit -> 'a1) -> (BitVector.bit ->
137 'a1) -> (BitVector.bitVector -> 'a1) -> 'a1 -> 'a1 -> 'a1 ->
138 (BitVector.byte -> 'a1) -> (BitVector.word -> 'a1) -> 'a1 -> 'a1 -> 'a1
139 -> 'a1 -> 'a1 -> (BitVector.byte -> 'a1) -> (BitVector.byte -> 'a1) ->
140 (BitVector.byte -> 'a1) -> (BitVector.word11 -> 'a1) -> (BitVector.word
141 -> 'a1) -> addressing_mode -> 'a1 **)
142 let rec addressing_mode_rect_Type5 h_DIRECT h_INDIRECT h_EXT_INDIRECT h_REGISTER h_ACC_A h_ACC_B h_DPTR h_DATA h_DATA16 h_ACC_DPTR h_ACC_PC h_EXT_INDIRECT_DPTR h_INDIRECT_DPTR h_CARRY h_BIT_ADDR h_N_BIT_ADDR h_RELATIVE h_ADDR11 h_ADDR16 = function
143 | DIRECT x_64 -> h_DIRECT x_64
144 | INDIRECT x_65 -> h_INDIRECT x_65
145 | EXT_INDIRECT x_66 -> h_EXT_INDIRECT x_66
146 | REGISTER x_67 -> h_REGISTER x_67
150 | DATA x_68 -> h_DATA x_68
151 | DATA16 x_69 -> h_DATA16 x_69
152 | ACC_DPTR -> h_ACC_DPTR
154 | EXT_INDIRECT_DPTR -> h_EXT_INDIRECT_DPTR
155 | INDIRECT_DPTR -> h_INDIRECT_DPTR
157 | BIT_ADDR x_70 -> h_BIT_ADDR x_70
158 | N_BIT_ADDR x_71 -> h_N_BIT_ADDR x_71
159 | RELATIVE x_72 -> h_RELATIVE x_72
160 | ADDR11 x_73 -> h_ADDR11 x_73
161 | ADDR16 x_74 -> h_ADDR16 x_74
163 (** val addressing_mode_rect_Type3 :
164 (BitVector.byte -> 'a1) -> (BitVector.bit -> 'a1) -> (BitVector.bit ->
165 'a1) -> (BitVector.bitVector -> 'a1) -> 'a1 -> 'a1 -> 'a1 ->
166 (BitVector.byte -> 'a1) -> (BitVector.word -> 'a1) -> 'a1 -> 'a1 -> 'a1
167 -> 'a1 -> 'a1 -> (BitVector.byte -> 'a1) -> (BitVector.byte -> 'a1) ->
168 (BitVector.byte -> 'a1) -> (BitVector.word11 -> 'a1) -> (BitVector.word
169 -> 'a1) -> addressing_mode -> 'a1 **)
170 let rec addressing_mode_rect_Type3 h_DIRECT h_INDIRECT h_EXT_INDIRECT h_REGISTER h_ACC_A h_ACC_B h_DPTR h_DATA h_DATA16 h_ACC_DPTR h_ACC_PC h_EXT_INDIRECT_DPTR h_INDIRECT_DPTR h_CARRY h_BIT_ADDR h_N_BIT_ADDR h_RELATIVE h_ADDR11 h_ADDR16 = function
171 | DIRECT x_95 -> h_DIRECT x_95
172 | INDIRECT x_96 -> h_INDIRECT x_96
173 | EXT_INDIRECT x_97 -> h_EXT_INDIRECT x_97
174 | REGISTER x_98 -> h_REGISTER x_98
178 | DATA x_99 -> h_DATA x_99
179 | DATA16 x_100 -> h_DATA16 x_100
180 | ACC_DPTR -> h_ACC_DPTR
182 | EXT_INDIRECT_DPTR -> h_EXT_INDIRECT_DPTR
183 | INDIRECT_DPTR -> h_INDIRECT_DPTR
185 | BIT_ADDR x_101 -> h_BIT_ADDR x_101
186 | N_BIT_ADDR x_102 -> h_N_BIT_ADDR x_102
187 | RELATIVE x_103 -> h_RELATIVE x_103
188 | ADDR11 x_104 -> h_ADDR11 x_104
189 | ADDR16 x_105 -> h_ADDR16 x_105
191 (** val addressing_mode_rect_Type2 :
192 (BitVector.byte -> 'a1) -> (BitVector.bit -> 'a1) -> (BitVector.bit ->
193 'a1) -> (BitVector.bitVector -> 'a1) -> 'a1 -> 'a1 -> 'a1 ->
194 (BitVector.byte -> 'a1) -> (BitVector.word -> 'a1) -> 'a1 -> 'a1 -> 'a1
195 -> 'a1 -> 'a1 -> (BitVector.byte -> 'a1) -> (BitVector.byte -> 'a1) ->
196 (BitVector.byte -> 'a1) -> (BitVector.word11 -> 'a1) -> (BitVector.word
197 -> 'a1) -> addressing_mode -> 'a1 **)
198 let rec addressing_mode_rect_Type2 h_DIRECT h_INDIRECT h_EXT_INDIRECT h_REGISTER h_ACC_A h_ACC_B h_DPTR h_DATA h_DATA16 h_ACC_DPTR h_ACC_PC h_EXT_INDIRECT_DPTR h_INDIRECT_DPTR h_CARRY h_BIT_ADDR h_N_BIT_ADDR h_RELATIVE h_ADDR11 h_ADDR16 = function
199 | DIRECT x_126 -> h_DIRECT x_126
200 | INDIRECT x_127 -> h_INDIRECT x_127
201 | EXT_INDIRECT x_128 -> h_EXT_INDIRECT x_128
202 | REGISTER x_129 -> h_REGISTER x_129
206 | DATA x_130 -> h_DATA x_130
207 | DATA16 x_131 -> h_DATA16 x_131
208 | ACC_DPTR -> h_ACC_DPTR
210 | EXT_INDIRECT_DPTR -> h_EXT_INDIRECT_DPTR
211 | INDIRECT_DPTR -> h_INDIRECT_DPTR
213 | BIT_ADDR x_132 -> h_BIT_ADDR x_132
214 | N_BIT_ADDR x_133 -> h_N_BIT_ADDR x_133
215 | RELATIVE x_134 -> h_RELATIVE x_134
216 | ADDR11 x_135 -> h_ADDR11 x_135
217 | ADDR16 x_136 -> h_ADDR16 x_136
219 (** val addressing_mode_rect_Type1 :
220 (BitVector.byte -> 'a1) -> (BitVector.bit -> 'a1) -> (BitVector.bit ->
221 'a1) -> (BitVector.bitVector -> 'a1) -> 'a1 -> 'a1 -> 'a1 ->
222 (BitVector.byte -> 'a1) -> (BitVector.word -> 'a1) -> 'a1 -> 'a1 -> 'a1
223 -> 'a1 -> 'a1 -> (BitVector.byte -> 'a1) -> (BitVector.byte -> 'a1) ->
224 (BitVector.byte -> 'a1) -> (BitVector.word11 -> 'a1) -> (BitVector.word
225 -> 'a1) -> addressing_mode -> 'a1 **)
226 let rec addressing_mode_rect_Type1 h_DIRECT h_INDIRECT h_EXT_INDIRECT h_REGISTER h_ACC_A h_ACC_B h_DPTR h_DATA h_DATA16 h_ACC_DPTR h_ACC_PC h_EXT_INDIRECT_DPTR h_INDIRECT_DPTR h_CARRY h_BIT_ADDR h_N_BIT_ADDR h_RELATIVE h_ADDR11 h_ADDR16 = function
227 | DIRECT x_157 -> h_DIRECT x_157
228 | INDIRECT x_158 -> h_INDIRECT x_158
229 | EXT_INDIRECT x_159 -> h_EXT_INDIRECT x_159
230 | REGISTER x_160 -> h_REGISTER x_160
234 | DATA x_161 -> h_DATA x_161
235 | DATA16 x_162 -> h_DATA16 x_162
236 | ACC_DPTR -> h_ACC_DPTR
238 | EXT_INDIRECT_DPTR -> h_EXT_INDIRECT_DPTR
239 | INDIRECT_DPTR -> h_INDIRECT_DPTR
241 | BIT_ADDR x_163 -> h_BIT_ADDR x_163
242 | N_BIT_ADDR x_164 -> h_N_BIT_ADDR x_164
243 | RELATIVE x_165 -> h_RELATIVE x_165
244 | ADDR11 x_166 -> h_ADDR11 x_166
245 | ADDR16 x_167 -> h_ADDR16 x_167
247 (** val addressing_mode_rect_Type0 :
248 (BitVector.byte -> 'a1) -> (BitVector.bit -> 'a1) -> (BitVector.bit ->
249 'a1) -> (BitVector.bitVector -> 'a1) -> 'a1 -> 'a1 -> 'a1 ->
250 (BitVector.byte -> 'a1) -> (BitVector.word -> 'a1) -> 'a1 -> 'a1 -> 'a1
251 -> 'a1 -> 'a1 -> (BitVector.byte -> 'a1) -> (BitVector.byte -> 'a1) ->
252 (BitVector.byte -> 'a1) -> (BitVector.word11 -> 'a1) -> (BitVector.word
253 -> 'a1) -> addressing_mode -> 'a1 **)
254 let rec addressing_mode_rect_Type0 h_DIRECT h_INDIRECT h_EXT_INDIRECT h_REGISTER h_ACC_A h_ACC_B h_DPTR h_DATA h_DATA16 h_ACC_DPTR h_ACC_PC h_EXT_INDIRECT_DPTR h_INDIRECT_DPTR h_CARRY h_BIT_ADDR h_N_BIT_ADDR h_RELATIVE h_ADDR11 h_ADDR16 = function
255 | DIRECT x_188 -> h_DIRECT x_188
256 | INDIRECT x_189 -> h_INDIRECT x_189
257 | EXT_INDIRECT x_190 -> h_EXT_INDIRECT x_190
258 | REGISTER x_191 -> h_REGISTER x_191
262 | DATA x_192 -> h_DATA x_192
263 | DATA16 x_193 -> h_DATA16 x_193
264 | ACC_DPTR -> h_ACC_DPTR
266 | EXT_INDIRECT_DPTR -> h_EXT_INDIRECT_DPTR
267 | INDIRECT_DPTR -> h_INDIRECT_DPTR
269 | BIT_ADDR x_194 -> h_BIT_ADDR x_194
270 | N_BIT_ADDR x_195 -> h_N_BIT_ADDR x_195
271 | RELATIVE x_196 -> h_RELATIVE x_196
272 | ADDR11 x_197 -> h_ADDR11 x_197
273 | ADDR16 x_198 -> h_ADDR16 x_198
275 (** val addressing_mode_inv_rect_Type4 :
276 addressing_mode -> (BitVector.byte -> __ -> 'a1) -> (BitVector.bit -> __
277 -> 'a1) -> (BitVector.bit -> __ -> 'a1) -> (BitVector.bitVector -> __ ->
278 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (BitVector.byte ->
279 __ -> 'a1) -> (BitVector.word -> __ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1)
280 -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (BitVector.byte -> __ ->
281 'a1) -> (BitVector.byte -> __ -> 'a1) -> (BitVector.byte -> __ -> 'a1) ->
282 (BitVector.word11 -> __ -> 'a1) -> (BitVector.word -> __ -> 'a1) -> 'a1 **)
283 let addressing_mode_inv_rect_Type4 hterm h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 =
285 addressing_mode_rect_Type4 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14
286 h15 h16 h17 h18 h19 hterm
290 (** val addressing_mode_inv_rect_Type3 :
291 addressing_mode -> (BitVector.byte -> __ -> 'a1) -> (BitVector.bit -> __
292 -> 'a1) -> (BitVector.bit -> __ -> 'a1) -> (BitVector.bitVector -> __ ->
293 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (BitVector.byte ->
294 __ -> 'a1) -> (BitVector.word -> __ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1)
295 -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (BitVector.byte -> __ ->
296 'a1) -> (BitVector.byte -> __ -> 'a1) -> (BitVector.byte -> __ -> 'a1) ->
297 (BitVector.word11 -> __ -> 'a1) -> (BitVector.word -> __ -> 'a1) -> 'a1 **)
298 let addressing_mode_inv_rect_Type3 hterm h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 =
300 addressing_mode_rect_Type3 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14
301 h15 h16 h17 h18 h19 hterm
305 (** val addressing_mode_inv_rect_Type2 :
306 addressing_mode -> (BitVector.byte -> __ -> 'a1) -> (BitVector.bit -> __
307 -> 'a1) -> (BitVector.bit -> __ -> 'a1) -> (BitVector.bitVector -> __ ->
308 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (BitVector.byte ->
309 __ -> 'a1) -> (BitVector.word -> __ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1)
310 -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (BitVector.byte -> __ ->
311 'a1) -> (BitVector.byte -> __ -> 'a1) -> (BitVector.byte -> __ -> 'a1) ->
312 (BitVector.word11 -> __ -> 'a1) -> (BitVector.word -> __ -> 'a1) -> 'a1 **)
313 let addressing_mode_inv_rect_Type2 hterm h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 =
315 addressing_mode_rect_Type2 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14
316 h15 h16 h17 h18 h19 hterm
320 (** val addressing_mode_inv_rect_Type1 :
321 addressing_mode -> (BitVector.byte -> __ -> 'a1) -> (BitVector.bit -> __
322 -> 'a1) -> (BitVector.bit -> __ -> 'a1) -> (BitVector.bitVector -> __ ->
323 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (BitVector.byte ->
324 __ -> 'a1) -> (BitVector.word -> __ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1)
325 -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (BitVector.byte -> __ ->
326 'a1) -> (BitVector.byte -> __ -> 'a1) -> (BitVector.byte -> __ -> 'a1) ->
327 (BitVector.word11 -> __ -> 'a1) -> (BitVector.word -> __ -> 'a1) -> 'a1 **)
328 let addressing_mode_inv_rect_Type1 hterm h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 =
330 addressing_mode_rect_Type1 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14
331 h15 h16 h17 h18 h19 hterm
335 (** val addressing_mode_inv_rect_Type0 :
336 addressing_mode -> (BitVector.byte -> __ -> 'a1) -> (BitVector.bit -> __
337 -> 'a1) -> (BitVector.bit -> __ -> 'a1) -> (BitVector.bitVector -> __ ->
338 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (BitVector.byte ->
339 __ -> 'a1) -> (BitVector.word -> __ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1)
340 -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (BitVector.byte -> __ ->
341 'a1) -> (BitVector.byte -> __ -> 'a1) -> (BitVector.byte -> __ -> 'a1) ->
342 (BitVector.word11 -> __ -> 'a1) -> (BitVector.word -> __ -> 'a1) -> 'a1 **)
343 let addressing_mode_inv_rect_Type0 hterm h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 =
345 addressing_mode_rect_Type0 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14
346 h15 h16 h17 h18 h19 hterm
350 (** val addressing_mode_discr : addressing_mode -> addressing_mode -> __ **)
351 let addressing_mode_discr x y =
352 Logic.eq_rect_Type2 x
354 | DIRECT a0 -> Obj.magic (fun _ dH -> dH __)
355 | INDIRECT a0 -> Obj.magic (fun _ dH -> dH __)
356 | EXT_INDIRECT a0 -> Obj.magic (fun _ dH -> dH __)
357 | REGISTER a0 -> Obj.magic (fun _ dH -> dH __)
358 | ACC_A -> Obj.magic (fun _ dH -> dH)
359 | ACC_B -> Obj.magic (fun _ dH -> dH)
360 | DPTR -> Obj.magic (fun _ dH -> dH)
361 | DATA a0 -> Obj.magic (fun _ dH -> dH __)
362 | DATA16 a0 -> Obj.magic (fun _ dH -> dH __)
363 | ACC_DPTR -> Obj.magic (fun _ dH -> dH)
364 | ACC_PC -> Obj.magic (fun _ dH -> dH)
365 | EXT_INDIRECT_DPTR -> Obj.magic (fun _ dH -> dH)
366 | INDIRECT_DPTR -> Obj.magic (fun _ dH -> dH)
367 | CARRY -> Obj.magic (fun _ dH -> dH)
368 | BIT_ADDR a0 -> Obj.magic (fun _ dH -> dH __)
369 | N_BIT_ADDR a0 -> Obj.magic (fun _ dH -> dH __)
370 | RELATIVE a0 -> Obj.magic (fun _ dH -> dH __)
371 | ADDR11 a0 -> Obj.magic (fun _ dH -> dH __)
372 | ADDR16 a0 -> Obj.magic (fun _ dH -> dH __)) y
374 (** val addressing_mode_jmdiscr :
375 addressing_mode -> addressing_mode -> __ **)
376 let addressing_mode_jmdiscr x y =
377 Logic.eq_rect_Type2 x
379 | DIRECT a0 -> Obj.magic (fun _ dH -> dH __)
380 | INDIRECT a0 -> Obj.magic (fun _ dH -> dH __)
381 | EXT_INDIRECT a0 -> Obj.magic (fun _ dH -> dH __)
382 | REGISTER a0 -> Obj.magic (fun _ dH -> dH __)
383 | ACC_A -> Obj.magic (fun _ dH -> dH)
384 | ACC_B -> Obj.magic (fun _ dH -> dH)
385 | DPTR -> Obj.magic (fun _ dH -> dH)
386 | DATA a0 -> Obj.magic (fun _ dH -> dH __)
387 | DATA16 a0 -> Obj.magic (fun _ dH -> dH __)
388 | ACC_DPTR -> Obj.magic (fun _ dH -> dH)
389 | ACC_PC -> Obj.magic (fun _ dH -> dH)
390 | EXT_INDIRECT_DPTR -> Obj.magic (fun _ dH -> dH)
391 | INDIRECT_DPTR -> Obj.magic (fun _ dH -> dH)
392 | CARRY -> Obj.magic (fun _ dH -> dH)
393 | BIT_ADDR a0 -> Obj.magic (fun _ dH -> dH __)
394 | N_BIT_ADDR a0 -> Obj.magic (fun _ dH -> dH __)
395 | RELATIVE a0 -> Obj.magic (fun _ dH -> dH __)
396 | ADDR11 a0 -> Obj.magic (fun _ dH -> dH __)
397 | ADDR16 a0 -> Obj.magic (fun _ dH -> dH __)) y
399 (** val eq_addressing_mode :
400 addressing_mode -> addressing_mode -> Bool.bool **)
401 let eq_addressing_mode a b =
406 BitVector.eq_bv (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
407 (Nat.S Nat.O)))))))) d e
408 | INDIRECT x -> Bool.False
409 | EXT_INDIRECT x -> Bool.False
410 | REGISTER x -> Bool.False
411 | ACC_A -> Bool.False
412 | ACC_B -> Bool.False
414 | DATA x -> Bool.False
415 | DATA16 x -> Bool.False
416 | ACC_DPTR -> Bool.False
417 | ACC_PC -> Bool.False
418 | EXT_INDIRECT_DPTR -> Bool.False
419 | INDIRECT_DPTR -> Bool.False
420 | CARRY -> Bool.False
421 | BIT_ADDR x -> Bool.False
422 | N_BIT_ADDR x -> Bool.False
423 | RELATIVE x -> Bool.False
424 | ADDR11 x -> Bool.False
425 | ADDR16 x -> Bool.False)
428 | DIRECT x -> Bool.False
429 | INDIRECT e -> BitVector.eq_b b' e
430 | EXT_INDIRECT x -> Bool.False
431 | REGISTER x -> Bool.False
432 | ACC_A -> Bool.False
433 | ACC_B -> Bool.False
435 | DATA x -> Bool.False
436 | DATA16 x -> Bool.False
437 | ACC_DPTR -> Bool.False
438 | ACC_PC -> Bool.False
439 | EXT_INDIRECT_DPTR -> Bool.False
440 | INDIRECT_DPTR -> Bool.False
441 | CARRY -> Bool.False
442 | BIT_ADDR x -> Bool.False
443 | N_BIT_ADDR x -> Bool.False
444 | RELATIVE x -> Bool.False
445 | ADDR11 x -> Bool.False
446 | ADDR16 x -> Bool.False)
449 | DIRECT x -> Bool.False
450 | INDIRECT x -> Bool.False
451 | EXT_INDIRECT e -> BitVector.eq_b b' e
452 | REGISTER x -> Bool.False
453 | ACC_A -> Bool.False
454 | ACC_B -> Bool.False
456 | DATA x -> Bool.False
457 | DATA16 x -> Bool.False
458 | ACC_DPTR -> Bool.False
459 | ACC_PC -> Bool.False
460 | EXT_INDIRECT_DPTR -> Bool.False
461 | INDIRECT_DPTR -> Bool.False
462 | CARRY -> Bool.False
463 | BIT_ADDR x -> Bool.False
464 | N_BIT_ADDR x -> Bool.False
465 | RELATIVE x -> Bool.False
466 | ADDR11 x -> Bool.False
467 | ADDR16 x -> Bool.False)
470 | DIRECT x -> Bool.False
471 | INDIRECT x -> Bool.False
472 | EXT_INDIRECT x -> Bool.False
473 | REGISTER bv' -> BitVector.eq_bv (Nat.S (Nat.S (Nat.S Nat.O))) bv bv'
474 | ACC_A -> Bool.False
475 | ACC_B -> Bool.False
477 | DATA x -> Bool.False
478 | DATA16 x -> Bool.False
479 | ACC_DPTR -> Bool.False
480 | ACC_PC -> Bool.False
481 | EXT_INDIRECT_DPTR -> Bool.False
482 | INDIRECT_DPTR -> Bool.False
483 | CARRY -> Bool.False
484 | BIT_ADDR x -> Bool.False
485 | N_BIT_ADDR x -> Bool.False
486 | RELATIVE x -> Bool.False
487 | ADDR11 x -> Bool.False
488 | ADDR16 x -> Bool.False)
491 | DIRECT x -> Bool.False
492 | INDIRECT x -> Bool.False
493 | EXT_INDIRECT x -> Bool.False
494 | REGISTER x -> Bool.False
496 | ACC_B -> Bool.False
498 | DATA x -> Bool.False
499 | DATA16 x -> Bool.False
500 | ACC_DPTR -> Bool.False
501 | ACC_PC -> Bool.False
502 | EXT_INDIRECT_DPTR -> Bool.False
503 | INDIRECT_DPTR -> Bool.False
504 | CARRY -> Bool.False
505 | BIT_ADDR x -> Bool.False
506 | N_BIT_ADDR x -> Bool.False
507 | RELATIVE x -> Bool.False
508 | ADDR11 x -> Bool.False
509 | ADDR16 x -> Bool.False)
512 | DIRECT x -> Bool.False
513 | INDIRECT x -> Bool.False
514 | EXT_INDIRECT x -> Bool.False
515 | REGISTER x -> Bool.False
516 | ACC_A -> Bool.False
519 | DATA x -> Bool.False
520 | DATA16 x -> Bool.False
521 | ACC_DPTR -> Bool.False
522 | ACC_PC -> Bool.False
523 | EXT_INDIRECT_DPTR -> Bool.False
524 | INDIRECT_DPTR -> Bool.False
525 | CARRY -> Bool.False
526 | BIT_ADDR x -> Bool.False
527 | N_BIT_ADDR x -> Bool.False
528 | RELATIVE x -> Bool.False
529 | ADDR11 x -> Bool.False
530 | ADDR16 x -> Bool.False)
533 | DIRECT x -> Bool.False
534 | INDIRECT x -> Bool.False
535 | EXT_INDIRECT x -> Bool.False
536 | REGISTER x -> Bool.False
537 | ACC_A -> Bool.False
538 | ACC_B -> Bool.False
540 | DATA x -> Bool.False
541 | DATA16 x -> Bool.False
542 | ACC_DPTR -> Bool.False
543 | ACC_PC -> Bool.False
544 | EXT_INDIRECT_DPTR -> Bool.False
545 | INDIRECT_DPTR -> Bool.False
546 | CARRY -> Bool.False
547 | BIT_ADDR x -> Bool.False
548 | N_BIT_ADDR x -> Bool.False
549 | RELATIVE x -> Bool.False
550 | ADDR11 x -> Bool.False
551 | ADDR16 x -> Bool.False)
554 | DIRECT x -> Bool.False
555 | INDIRECT x -> Bool.False
556 | EXT_INDIRECT x -> Bool.False
557 | REGISTER x -> Bool.False
558 | ACC_A -> Bool.False
559 | ACC_B -> Bool.False
562 BitVector.eq_bv (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
563 (Nat.S Nat.O)))))))) b' e
564 | DATA16 x -> Bool.False
565 | ACC_DPTR -> Bool.False
566 | ACC_PC -> Bool.False
567 | EXT_INDIRECT_DPTR -> Bool.False
568 | INDIRECT_DPTR -> Bool.False
569 | CARRY -> Bool.False
570 | BIT_ADDR x -> Bool.False
571 | N_BIT_ADDR x -> Bool.False
572 | RELATIVE x -> Bool.False
573 | ADDR11 x -> Bool.False
574 | ADDR16 x -> Bool.False)
577 | DIRECT x -> Bool.False
578 | INDIRECT x -> Bool.False
579 | EXT_INDIRECT x -> Bool.False
580 | REGISTER x -> Bool.False
581 | ACC_A -> Bool.False
582 | ACC_B -> Bool.False
584 | DATA x -> Bool.False
586 BitVector.eq_bv (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
587 (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
588 Nat.O)))))))))))))))) w e
589 | ACC_DPTR -> Bool.False
590 | ACC_PC -> Bool.False
591 | EXT_INDIRECT_DPTR -> Bool.False
592 | INDIRECT_DPTR -> Bool.False
593 | CARRY -> Bool.False
594 | BIT_ADDR x -> Bool.False
595 | N_BIT_ADDR x -> Bool.False
596 | RELATIVE x -> Bool.False
597 | ADDR11 x -> Bool.False
598 | ADDR16 x -> Bool.False)
601 | DIRECT x -> Bool.False
602 | INDIRECT x -> Bool.False
603 | EXT_INDIRECT x -> Bool.False
604 | REGISTER x -> Bool.False
605 | ACC_A -> Bool.False
606 | ACC_B -> Bool.False
608 | DATA x -> Bool.False
609 | DATA16 x -> Bool.False
610 | ACC_DPTR -> Bool.True
611 | ACC_PC -> Bool.False
612 | EXT_INDIRECT_DPTR -> Bool.False
613 | INDIRECT_DPTR -> Bool.False
614 | CARRY -> Bool.False
615 | BIT_ADDR x -> Bool.False
616 | N_BIT_ADDR x -> Bool.False
617 | RELATIVE x -> Bool.False
618 | ADDR11 x -> Bool.False
619 | ADDR16 x -> Bool.False)
622 | DIRECT x -> Bool.False
623 | INDIRECT x -> Bool.False
624 | EXT_INDIRECT x -> Bool.False
625 | REGISTER x -> Bool.False
626 | ACC_A -> Bool.False
627 | ACC_B -> Bool.False
629 | DATA x -> Bool.False
630 | DATA16 x -> Bool.False
631 | ACC_DPTR -> Bool.False
632 | ACC_PC -> Bool.True
633 | EXT_INDIRECT_DPTR -> Bool.False
634 | INDIRECT_DPTR -> Bool.False
635 | CARRY -> Bool.False
636 | BIT_ADDR x -> Bool.False
637 | N_BIT_ADDR x -> Bool.False
638 | RELATIVE x -> Bool.False
639 | ADDR11 x -> Bool.False
640 | ADDR16 x -> Bool.False)
641 | EXT_INDIRECT_DPTR ->
643 | DIRECT x -> Bool.False
644 | INDIRECT x -> Bool.False
645 | EXT_INDIRECT x -> Bool.False
646 | REGISTER x -> Bool.False
647 | ACC_A -> Bool.False
648 | ACC_B -> Bool.False
650 | DATA x -> Bool.False
651 | DATA16 x -> Bool.False
652 | ACC_DPTR -> Bool.False
653 | ACC_PC -> Bool.False
654 | EXT_INDIRECT_DPTR -> Bool.True
655 | INDIRECT_DPTR -> Bool.False
656 | CARRY -> Bool.False
657 | BIT_ADDR x -> Bool.False
658 | N_BIT_ADDR x -> Bool.False
659 | RELATIVE x -> Bool.False
660 | ADDR11 x -> Bool.False
661 | ADDR16 x -> Bool.False)
664 | DIRECT x -> Bool.False
665 | INDIRECT x -> Bool.False
666 | EXT_INDIRECT x -> Bool.False
667 | REGISTER x -> Bool.False
668 | ACC_A -> Bool.False
669 | ACC_B -> Bool.False
671 | DATA x -> Bool.False
672 | DATA16 x -> Bool.False
673 | ACC_DPTR -> Bool.False
674 | ACC_PC -> Bool.False
675 | EXT_INDIRECT_DPTR -> Bool.False
676 | INDIRECT_DPTR -> Bool.True
677 | CARRY -> Bool.False
678 | BIT_ADDR x -> Bool.False
679 | N_BIT_ADDR x -> Bool.False
680 | RELATIVE x -> Bool.False
681 | ADDR11 x -> Bool.False
682 | ADDR16 x -> Bool.False)
685 | DIRECT x -> Bool.False
686 | INDIRECT x -> Bool.False
687 | EXT_INDIRECT x -> Bool.False
688 | REGISTER x -> Bool.False
689 | ACC_A -> Bool.False
690 | ACC_B -> Bool.False
692 | DATA x -> Bool.False
693 | DATA16 x -> Bool.False
694 | ACC_DPTR -> Bool.False
695 | ACC_PC -> Bool.False
696 | EXT_INDIRECT_DPTR -> Bool.False
697 | INDIRECT_DPTR -> Bool.False
699 | BIT_ADDR x -> Bool.False
700 | N_BIT_ADDR x -> Bool.False
701 | RELATIVE x -> Bool.False
702 | ADDR11 x -> Bool.False
703 | ADDR16 x -> Bool.False)
706 | DIRECT x -> Bool.False
707 | INDIRECT x -> Bool.False
708 | EXT_INDIRECT x -> Bool.False
709 | REGISTER x -> Bool.False
710 | ACC_A -> Bool.False
711 | ACC_B -> Bool.False
713 | DATA x -> Bool.False
714 | DATA16 x -> Bool.False
715 | ACC_DPTR -> Bool.False
716 | ACC_PC -> Bool.False
717 | EXT_INDIRECT_DPTR -> Bool.False
718 | INDIRECT_DPTR -> Bool.False
719 | CARRY -> Bool.False
721 BitVector.eq_bv (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
722 (Nat.S Nat.O)))))))) b' e
723 | N_BIT_ADDR x -> Bool.False
724 | RELATIVE x -> Bool.False
725 | ADDR11 x -> Bool.False
726 | ADDR16 x -> Bool.False)
729 | DIRECT x -> Bool.False
730 | INDIRECT x -> Bool.False
731 | EXT_INDIRECT x -> Bool.False
732 | REGISTER x -> Bool.False
733 | ACC_A -> Bool.False
734 | ACC_B -> Bool.False
736 | DATA x -> Bool.False
737 | DATA16 x -> Bool.False
738 | ACC_DPTR -> Bool.False
739 | ACC_PC -> Bool.False
740 | EXT_INDIRECT_DPTR -> Bool.False
741 | INDIRECT_DPTR -> Bool.False
742 | CARRY -> Bool.False
743 | BIT_ADDR x -> Bool.False
745 BitVector.eq_bv (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
746 (Nat.S Nat.O)))))))) b' e
747 | RELATIVE x -> Bool.False
748 | ADDR11 x -> Bool.False
749 | ADDR16 x -> Bool.False)
752 | DIRECT x -> Bool.False
753 | INDIRECT x -> Bool.False
754 | EXT_INDIRECT x -> Bool.False
755 | REGISTER x -> Bool.False
756 | ACC_A -> Bool.False
757 | ACC_B -> Bool.False
759 | DATA x -> Bool.False
760 | DATA16 x -> Bool.False
761 | ACC_DPTR -> Bool.False
762 | ACC_PC -> Bool.False
763 | EXT_INDIRECT_DPTR -> Bool.False
764 | INDIRECT_DPTR -> Bool.False
765 | CARRY -> Bool.False
766 | BIT_ADDR x -> Bool.False
767 | N_BIT_ADDR x -> Bool.False
769 BitVector.eq_bv (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
770 (Nat.S Nat.O)))))))) n e
771 | ADDR11 x -> Bool.False
772 | ADDR16 x -> Bool.False)
775 | DIRECT x -> Bool.False
776 | INDIRECT x -> Bool.False
777 | EXT_INDIRECT x -> Bool.False
778 | REGISTER x -> Bool.False
779 | ACC_A -> Bool.False
780 | ACC_B -> Bool.False
782 | DATA x -> Bool.False
783 | DATA16 x -> Bool.False
784 | ACC_DPTR -> Bool.False
785 | ACC_PC -> Bool.False
786 | EXT_INDIRECT_DPTR -> Bool.False
787 | INDIRECT_DPTR -> Bool.False
788 | CARRY -> Bool.False
789 | BIT_ADDR x -> Bool.False
790 | N_BIT_ADDR x -> Bool.False
791 | RELATIVE x -> Bool.False
793 BitVector.eq_bv (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
794 (Nat.S (Nat.S (Nat.S (Nat.S Nat.O))))))))))) w e
795 | ADDR16 x -> Bool.False)
798 | DIRECT x -> Bool.False
799 | INDIRECT x -> Bool.False
800 | EXT_INDIRECT x -> Bool.False
801 | REGISTER x -> Bool.False
802 | ACC_A -> Bool.False
803 | ACC_B -> Bool.False
805 | DATA x -> Bool.False
806 | DATA16 x -> Bool.False
807 | ACC_DPTR -> Bool.False
808 | ACC_PC -> Bool.False
809 | EXT_INDIRECT_DPTR -> Bool.False
810 | INDIRECT_DPTR -> Bool.False
811 | CARRY -> Bool.False
812 | BIT_ADDR x -> Bool.False
813 | N_BIT_ADDR x -> Bool.False
814 | RELATIVE x -> Bool.False
815 | ADDR11 x -> Bool.False
817 BitVector.eq_bv (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
818 (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
819 Nat.O)))))))))))))))) w e)
821 type addressing_mode_tag =
842 (** val addressing_mode_tag_rect_Type4 :
843 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1
844 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 ->
845 addressing_mode_tag -> 'a1 **)
846 let rec addressing_mode_tag_rect_Type4 h_direct h_indirect h_ext_indirect h_registr h_acc_a h_acc_b h_dptr h_data h_data16 h_acc_dptr h_acc_pc h_ext_indirect_dptr h_indirect_dptr h_carry h_bit_addr h_n_bit_addr h_relative h_addr11 h_addr16 = function
848 | Indirect -> h_indirect
849 | Ext_indirect -> h_ext_indirect
850 | Registr -> h_registr
856 | Acc_dptr -> h_acc_dptr
858 | Ext_indirect_dptr -> h_ext_indirect_dptr
859 | Indirect_dptr -> h_indirect_dptr
861 | Bit_addr -> h_bit_addr
862 | N_bit_addr -> h_n_bit_addr
863 | Relative -> h_relative
867 (** val addressing_mode_tag_rect_Type5 :
868 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1
869 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 ->
870 addressing_mode_tag -> 'a1 **)
871 let rec addressing_mode_tag_rect_Type5 h_direct h_indirect h_ext_indirect h_registr h_acc_a h_acc_b h_dptr h_data h_data16 h_acc_dptr h_acc_pc h_ext_indirect_dptr h_indirect_dptr h_carry h_bit_addr h_n_bit_addr h_relative h_addr11 h_addr16 = function
873 | Indirect -> h_indirect
874 | Ext_indirect -> h_ext_indirect
875 | Registr -> h_registr
881 | Acc_dptr -> h_acc_dptr
883 | Ext_indirect_dptr -> h_ext_indirect_dptr
884 | Indirect_dptr -> h_indirect_dptr
886 | Bit_addr -> h_bit_addr
887 | N_bit_addr -> h_n_bit_addr
888 | Relative -> h_relative
892 (** val addressing_mode_tag_rect_Type3 :
893 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1
894 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 ->
895 addressing_mode_tag -> 'a1 **)
896 let rec addressing_mode_tag_rect_Type3 h_direct h_indirect h_ext_indirect h_registr h_acc_a h_acc_b h_dptr h_data h_data16 h_acc_dptr h_acc_pc h_ext_indirect_dptr h_indirect_dptr h_carry h_bit_addr h_n_bit_addr h_relative h_addr11 h_addr16 = function
898 | Indirect -> h_indirect
899 | Ext_indirect -> h_ext_indirect
900 | Registr -> h_registr
906 | Acc_dptr -> h_acc_dptr
908 | Ext_indirect_dptr -> h_ext_indirect_dptr
909 | Indirect_dptr -> h_indirect_dptr
911 | Bit_addr -> h_bit_addr
912 | N_bit_addr -> h_n_bit_addr
913 | Relative -> h_relative
917 (** val addressing_mode_tag_rect_Type2 :
918 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1
919 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 ->
920 addressing_mode_tag -> 'a1 **)
921 let rec addressing_mode_tag_rect_Type2 h_direct h_indirect h_ext_indirect h_registr h_acc_a h_acc_b h_dptr h_data h_data16 h_acc_dptr h_acc_pc h_ext_indirect_dptr h_indirect_dptr h_carry h_bit_addr h_n_bit_addr h_relative h_addr11 h_addr16 = function
923 | Indirect -> h_indirect
924 | Ext_indirect -> h_ext_indirect
925 | Registr -> h_registr
931 | Acc_dptr -> h_acc_dptr
933 | Ext_indirect_dptr -> h_ext_indirect_dptr
934 | Indirect_dptr -> h_indirect_dptr
936 | Bit_addr -> h_bit_addr
937 | N_bit_addr -> h_n_bit_addr
938 | Relative -> h_relative
942 (** val addressing_mode_tag_rect_Type1 :
943 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1
944 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 ->
945 addressing_mode_tag -> 'a1 **)
946 let rec addressing_mode_tag_rect_Type1 h_direct h_indirect h_ext_indirect h_registr h_acc_a h_acc_b h_dptr h_data h_data16 h_acc_dptr h_acc_pc h_ext_indirect_dptr h_indirect_dptr h_carry h_bit_addr h_n_bit_addr h_relative h_addr11 h_addr16 = function
948 | Indirect -> h_indirect
949 | Ext_indirect -> h_ext_indirect
950 | Registr -> h_registr
956 | Acc_dptr -> h_acc_dptr
958 | Ext_indirect_dptr -> h_ext_indirect_dptr
959 | Indirect_dptr -> h_indirect_dptr
961 | Bit_addr -> h_bit_addr
962 | N_bit_addr -> h_n_bit_addr
963 | Relative -> h_relative
967 (** val addressing_mode_tag_rect_Type0 :
968 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1
969 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 -> 'a1 ->
970 addressing_mode_tag -> 'a1 **)
971 let rec addressing_mode_tag_rect_Type0 h_direct h_indirect h_ext_indirect h_registr h_acc_a h_acc_b h_dptr h_data h_data16 h_acc_dptr h_acc_pc h_ext_indirect_dptr h_indirect_dptr h_carry h_bit_addr h_n_bit_addr h_relative h_addr11 h_addr16 = function
973 | Indirect -> h_indirect
974 | Ext_indirect -> h_ext_indirect
975 | Registr -> h_registr
981 | Acc_dptr -> h_acc_dptr
983 | Ext_indirect_dptr -> h_ext_indirect_dptr
984 | Indirect_dptr -> h_indirect_dptr
986 | Bit_addr -> h_bit_addr
987 | N_bit_addr -> h_n_bit_addr
988 | Relative -> h_relative
992 (** val addressing_mode_tag_inv_rect_Type4 :
993 addressing_mode_tag -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__
994 -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) ->
995 (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1)
996 -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ ->
997 'a1) -> (__ -> 'a1) -> 'a1 **)
998 let addressing_mode_tag_inv_rect_Type4 hterm h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 =
1000 addressing_mode_tag_rect_Type4 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13
1001 h14 h15 h16 h17 h18 h19 hterm
1005 (** val addressing_mode_tag_inv_rect_Type3 :
1006 addressing_mode_tag -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__
1007 -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) ->
1008 (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1)
1009 -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ ->
1010 'a1) -> (__ -> 'a1) -> 'a1 **)
1011 let addressing_mode_tag_inv_rect_Type3 hterm h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 =
1013 addressing_mode_tag_rect_Type3 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13
1014 h14 h15 h16 h17 h18 h19 hterm
1018 (** val addressing_mode_tag_inv_rect_Type2 :
1019 addressing_mode_tag -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__
1020 -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) ->
1021 (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1)
1022 -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ ->
1023 'a1) -> (__ -> 'a1) -> 'a1 **)
1024 let addressing_mode_tag_inv_rect_Type2 hterm h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 =
1026 addressing_mode_tag_rect_Type2 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13
1027 h14 h15 h16 h17 h18 h19 hterm
1031 (** val addressing_mode_tag_inv_rect_Type1 :
1032 addressing_mode_tag -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__
1033 -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) ->
1034 (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1)
1035 -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ ->
1036 'a1) -> (__ -> 'a1) -> 'a1 **)
1037 let addressing_mode_tag_inv_rect_Type1 hterm h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 =
1039 addressing_mode_tag_rect_Type1 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13
1040 h14 h15 h16 h17 h18 h19 hterm
1044 (** val addressing_mode_tag_inv_rect_Type0 :
1045 addressing_mode_tag -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__
1046 -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) ->
1047 (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1)
1048 -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ -> 'a1) -> (__ ->
1049 'a1) -> (__ -> 'a1) -> 'a1 **)
1050 let addressing_mode_tag_inv_rect_Type0 hterm h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 =
1052 addressing_mode_tag_rect_Type0 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13
1053 h14 h15 h16 h17 h18 h19 hterm
1057 (** val addressing_mode_tag_discr :
1058 addressing_mode_tag -> addressing_mode_tag -> __ **)
1059 let addressing_mode_tag_discr x y =
1060 Logic.eq_rect_Type2 x
1062 | Direct -> Obj.magic (fun _ dH -> dH)
1063 | Indirect -> Obj.magic (fun _ dH -> dH)
1064 | Ext_indirect -> Obj.magic (fun _ dH -> dH)
1065 | Registr -> Obj.magic (fun _ dH -> dH)
1066 | Acc_a -> Obj.magic (fun _ dH -> dH)
1067 | Acc_b -> Obj.magic (fun _ dH -> dH)
1068 | Dptr -> Obj.magic (fun _ dH -> dH)
1069 | Data -> Obj.magic (fun _ dH -> dH)
1070 | Data16 -> Obj.magic (fun _ dH -> dH)
1071 | Acc_dptr -> Obj.magic (fun _ dH -> dH)
1072 | Acc_pc -> Obj.magic (fun _ dH -> dH)
1073 | Ext_indirect_dptr -> Obj.magic (fun _ dH -> dH)
1074 | Indirect_dptr -> Obj.magic (fun _ dH -> dH)
1075 | Carry -> Obj.magic (fun _ dH -> dH)
1076 | Bit_addr -> Obj.magic (fun _ dH -> dH)
1077 | N_bit_addr -> Obj.magic (fun _ dH -> dH)
1078 | Relative -> Obj.magic (fun _ dH -> dH)
1079 | Addr11 -> Obj.magic (fun _ dH -> dH)
1080 | Addr16 -> Obj.magic (fun _ dH -> dH)) y
1082 (** val addressing_mode_tag_jmdiscr :
1083 addressing_mode_tag -> addressing_mode_tag -> __ **)
1084 let addressing_mode_tag_jmdiscr x y =
1085 Logic.eq_rect_Type2 x
1087 | Direct -> Obj.magic (fun _ dH -> dH)
1088 | Indirect -> Obj.magic (fun _ dH -> dH)
1089 | Ext_indirect -> Obj.magic (fun _ dH -> dH)
1090 | Registr -> Obj.magic (fun _ dH -> dH)
1091 | Acc_a -> Obj.magic (fun _ dH -> dH)
1092 | Acc_b -> Obj.magic (fun _ dH -> dH)
1093 | Dptr -> Obj.magic (fun _ dH -> dH)
1094 | Data -> Obj.magic (fun _ dH -> dH)
1095 | Data16 -> Obj.magic (fun _ dH -> dH)
1096 | Acc_dptr -> Obj.magic (fun _ dH -> dH)
1097 | Acc_pc -> Obj.magic (fun _ dH -> dH)
1098 | Ext_indirect_dptr -> Obj.magic (fun _ dH -> dH)
1099 | Indirect_dptr -> Obj.magic (fun _ dH -> dH)
1100 | Carry -> Obj.magic (fun _ dH -> dH)
1101 | Bit_addr -> Obj.magic (fun _ dH -> dH)
1102 | N_bit_addr -> Obj.magic (fun _ dH -> dH)
1103 | Relative -> Obj.magic (fun _ dH -> dH)
1104 | Addr11 -> Obj.magic (fun _ dH -> dH)
1105 | Addr16 -> Obj.magic (fun _ dH -> dH)) y
1107 (** val eq_a : addressing_mode_tag -> addressing_mode_tag -> Bool.bool **)
1112 | Direct -> Bool.True
1113 | Indirect -> Bool.False
1114 | Ext_indirect -> Bool.False
1115 | Registr -> Bool.False
1116 | Acc_a -> Bool.False
1117 | Acc_b -> Bool.False
1118 | Dptr -> Bool.False
1119 | Data -> Bool.False
1120 | Data16 -> Bool.False
1121 | Acc_dptr -> Bool.False
1122 | Acc_pc -> Bool.False
1123 | Ext_indirect_dptr -> Bool.False
1124 | Indirect_dptr -> Bool.False
1125 | Carry -> Bool.False
1126 | Bit_addr -> Bool.False
1127 | N_bit_addr -> Bool.False
1128 | Relative -> Bool.False
1129 | Addr11 -> Bool.False
1130 | Addr16 -> Bool.False)
1133 | Direct -> Bool.False
1134 | Indirect -> Bool.True
1135 | Ext_indirect -> Bool.False
1136 | Registr -> Bool.False
1137 | Acc_a -> Bool.False
1138 | Acc_b -> Bool.False
1139 | Dptr -> Bool.False
1140 | Data -> Bool.False
1141 | Data16 -> Bool.False
1142 | Acc_dptr -> Bool.False
1143 | Acc_pc -> Bool.False
1144 | Ext_indirect_dptr -> Bool.False
1145 | Indirect_dptr -> Bool.False
1146 | Carry -> Bool.False
1147 | Bit_addr -> Bool.False
1148 | N_bit_addr -> Bool.False
1149 | Relative -> Bool.False
1150 | Addr11 -> Bool.False
1151 | Addr16 -> Bool.False)
1154 | Direct -> Bool.False
1155 | Indirect -> Bool.False
1156 | Ext_indirect -> Bool.True
1157 | Registr -> Bool.False
1158 | Acc_a -> Bool.False
1159 | Acc_b -> Bool.False
1160 | Dptr -> Bool.False
1161 | Data -> Bool.False
1162 | Data16 -> Bool.False
1163 | Acc_dptr -> Bool.False
1164 | Acc_pc -> Bool.False
1165 | Ext_indirect_dptr -> Bool.False
1166 | Indirect_dptr -> Bool.False
1167 | Carry -> Bool.False
1168 | Bit_addr -> Bool.False
1169 | N_bit_addr -> Bool.False
1170 | Relative -> Bool.False
1171 | Addr11 -> Bool.False
1172 | Addr16 -> Bool.False)
1175 | Direct -> Bool.False
1176 | Indirect -> Bool.False
1177 | Ext_indirect -> Bool.False
1178 | Registr -> Bool.True
1179 | Acc_a -> Bool.False
1180 | Acc_b -> Bool.False
1181 | Dptr -> Bool.False
1182 | Data -> Bool.False
1183 | Data16 -> Bool.False
1184 | Acc_dptr -> Bool.False
1185 | Acc_pc -> Bool.False
1186 | Ext_indirect_dptr -> Bool.False
1187 | Indirect_dptr -> Bool.False
1188 | Carry -> Bool.False
1189 | Bit_addr -> Bool.False
1190 | N_bit_addr -> Bool.False
1191 | Relative -> Bool.False
1192 | Addr11 -> Bool.False
1193 | Addr16 -> Bool.False)
1196 | Direct -> Bool.False
1197 | Indirect -> Bool.False
1198 | Ext_indirect -> Bool.False
1199 | Registr -> Bool.False
1200 | Acc_a -> Bool.True
1201 | Acc_b -> Bool.False
1202 | Dptr -> Bool.False
1203 | Data -> Bool.False
1204 | Data16 -> Bool.False
1205 | Acc_dptr -> Bool.False
1206 | Acc_pc -> Bool.False
1207 | Ext_indirect_dptr -> Bool.False
1208 | Indirect_dptr -> Bool.False
1209 | Carry -> Bool.False
1210 | Bit_addr -> Bool.False
1211 | N_bit_addr -> Bool.False
1212 | Relative -> Bool.False
1213 | Addr11 -> Bool.False
1214 | Addr16 -> Bool.False)
1217 | Direct -> Bool.False
1218 | Indirect -> Bool.False
1219 | Ext_indirect -> Bool.False
1220 | Registr -> Bool.False
1221 | Acc_a -> Bool.False
1222 | Acc_b -> Bool.True
1223 | Dptr -> Bool.False
1224 | Data -> Bool.False
1225 | Data16 -> Bool.False
1226 | Acc_dptr -> Bool.False
1227 | Acc_pc -> Bool.False
1228 | Ext_indirect_dptr -> Bool.False
1229 | Indirect_dptr -> Bool.False
1230 | Carry -> Bool.False
1231 | Bit_addr -> Bool.False
1232 | N_bit_addr -> Bool.False
1233 | Relative -> Bool.False
1234 | Addr11 -> Bool.False
1235 | Addr16 -> Bool.False)
1238 | Direct -> Bool.False
1239 | Indirect -> Bool.False
1240 | Ext_indirect -> Bool.False
1241 | Registr -> Bool.False
1242 | Acc_a -> Bool.False
1243 | Acc_b -> Bool.False
1245 | Data -> Bool.False
1246 | Data16 -> Bool.False
1247 | Acc_dptr -> Bool.False
1248 | Acc_pc -> Bool.False
1249 | Ext_indirect_dptr -> Bool.False
1250 | Indirect_dptr -> Bool.False
1251 | Carry -> Bool.False
1252 | Bit_addr -> Bool.False
1253 | N_bit_addr -> Bool.False
1254 | Relative -> Bool.False
1255 | Addr11 -> Bool.False
1256 | Addr16 -> Bool.False)
1259 | Direct -> Bool.False
1260 | Indirect -> Bool.False
1261 | Ext_indirect -> Bool.False
1262 | Registr -> Bool.False
1263 | Acc_a -> Bool.False
1264 | Acc_b -> Bool.False
1265 | Dptr -> Bool.False
1267 | Data16 -> Bool.False
1268 | Acc_dptr -> Bool.False
1269 | Acc_pc -> Bool.False
1270 | Ext_indirect_dptr -> Bool.False
1271 | Indirect_dptr -> Bool.False
1272 | Carry -> Bool.False
1273 | Bit_addr -> Bool.False
1274 | N_bit_addr -> Bool.False
1275 | Relative -> Bool.False
1276 | Addr11 -> Bool.False
1277 | Addr16 -> Bool.False)
1280 | Direct -> Bool.False
1281 | Indirect -> Bool.False
1282 | Ext_indirect -> Bool.False
1283 | Registr -> Bool.False
1284 | Acc_a -> Bool.False
1285 | Acc_b -> Bool.False
1286 | Dptr -> Bool.False
1287 | Data -> Bool.False
1288 | Data16 -> Bool.True
1289 | Acc_dptr -> Bool.False
1290 | Acc_pc -> Bool.False
1291 | Ext_indirect_dptr -> Bool.False
1292 | Indirect_dptr -> Bool.False
1293 | Carry -> Bool.False
1294 | Bit_addr -> Bool.False
1295 | N_bit_addr -> Bool.False
1296 | Relative -> Bool.False
1297 | Addr11 -> Bool.False
1298 | Addr16 -> Bool.False)
1301 | Direct -> Bool.False
1302 | Indirect -> Bool.False
1303 | Ext_indirect -> Bool.False
1304 | Registr -> Bool.False
1305 | Acc_a -> Bool.False
1306 | Acc_b -> Bool.False
1307 | Dptr -> Bool.False
1308 | Data -> Bool.False
1309 | Data16 -> Bool.False
1310 | Acc_dptr -> Bool.True
1311 | Acc_pc -> Bool.False
1312 | Ext_indirect_dptr -> Bool.False
1313 | Indirect_dptr -> Bool.False
1314 | Carry -> Bool.False
1315 | Bit_addr -> Bool.False
1316 | N_bit_addr -> Bool.False
1317 | Relative -> Bool.False
1318 | Addr11 -> Bool.False
1319 | Addr16 -> Bool.False)
1322 | Direct -> Bool.False
1323 | Indirect -> Bool.False
1324 | Ext_indirect -> Bool.False
1325 | Registr -> Bool.False
1326 | Acc_a -> Bool.False
1327 | Acc_b -> Bool.False
1328 | Dptr -> Bool.False
1329 | Data -> Bool.False
1330 | Data16 -> Bool.False
1331 | Acc_dptr -> Bool.False
1332 | Acc_pc -> Bool.True
1333 | Ext_indirect_dptr -> Bool.False
1334 | Indirect_dptr -> Bool.False
1335 | Carry -> Bool.False
1336 | Bit_addr -> Bool.False
1337 | N_bit_addr -> Bool.False
1338 | Relative -> Bool.False
1339 | Addr11 -> Bool.False
1340 | Addr16 -> Bool.False)
1341 | Ext_indirect_dptr ->
1343 | Direct -> Bool.False
1344 | Indirect -> Bool.False
1345 | Ext_indirect -> Bool.False
1346 | Registr -> Bool.False
1347 | Acc_a -> Bool.False
1348 | Acc_b -> Bool.False
1349 | Dptr -> Bool.False
1350 | Data -> Bool.False
1351 | Data16 -> Bool.False
1352 | Acc_dptr -> Bool.False
1353 | Acc_pc -> Bool.False
1354 | Ext_indirect_dptr -> Bool.True
1355 | Indirect_dptr -> Bool.False
1356 | Carry -> Bool.False
1357 | Bit_addr -> Bool.False
1358 | N_bit_addr -> Bool.False
1359 | Relative -> Bool.False
1360 | Addr11 -> Bool.False
1361 | Addr16 -> Bool.False)
1364 | Direct -> Bool.False
1365 | Indirect -> Bool.False
1366 | Ext_indirect -> Bool.False
1367 | Registr -> Bool.False
1368 | Acc_a -> Bool.False
1369 | Acc_b -> Bool.False
1370 | Dptr -> Bool.False
1371 | Data -> Bool.False
1372 | Data16 -> Bool.False
1373 | Acc_dptr -> Bool.False
1374 | Acc_pc -> Bool.False
1375 | Ext_indirect_dptr -> Bool.False
1376 | Indirect_dptr -> Bool.True
1377 | Carry -> Bool.False
1378 | Bit_addr -> Bool.False
1379 | N_bit_addr -> Bool.False
1380 | Relative -> Bool.False
1381 | Addr11 -> Bool.False
1382 | Addr16 -> Bool.False)
1385 | Direct -> Bool.False
1386 | Indirect -> Bool.False
1387 | Ext_indirect -> Bool.False
1388 | Registr -> Bool.False
1389 | Acc_a -> Bool.False
1390 | Acc_b -> Bool.False
1391 | Dptr -> Bool.False
1392 | Data -> Bool.False
1393 | Data16 -> Bool.False
1394 | Acc_dptr -> Bool.False
1395 | Acc_pc -> Bool.False
1396 | Ext_indirect_dptr -> Bool.False
1397 | Indirect_dptr -> Bool.False
1398 | Carry -> Bool.True
1399 | Bit_addr -> Bool.False
1400 | N_bit_addr -> Bool.False
1401 | Relative -> Bool.False
1402 | Addr11 -> Bool.False
1403 | Addr16 -> Bool.False)
1406 | Direct -> Bool.False
1407 | Indirect -> Bool.False
1408 | Ext_indirect -> Bool.False
1409 | Registr -> Bool.False
1410 | Acc_a -> Bool.False
1411 | Acc_b -> Bool.False
1412 | Dptr -> Bool.False
1413 | Data -> Bool.False
1414 | Data16 -> Bool.False
1415 | Acc_dptr -> Bool.False
1416 | Acc_pc -> Bool.False
1417 | Ext_indirect_dptr -> Bool.False
1418 | Indirect_dptr -> Bool.False
1419 | Carry -> Bool.False
1420 | Bit_addr -> Bool.True
1421 | N_bit_addr -> Bool.False
1422 | Relative -> Bool.False
1423 | Addr11 -> Bool.False
1424 | Addr16 -> Bool.False)
1427 | Direct -> Bool.False
1428 | Indirect -> Bool.False
1429 | Ext_indirect -> Bool.False
1430 | Registr -> Bool.False
1431 | Acc_a -> Bool.False
1432 | Acc_b -> Bool.False
1433 | Dptr -> Bool.False
1434 | Data -> Bool.False
1435 | Data16 -> Bool.False
1436 | Acc_dptr -> Bool.False
1437 | Acc_pc -> Bool.False
1438 | Ext_indirect_dptr -> Bool.False
1439 | Indirect_dptr -> Bool.False
1440 | Carry -> Bool.False
1441 | Bit_addr -> Bool.False
1442 | N_bit_addr -> Bool.True
1443 | Relative -> Bool.False
1444 | Addr11 -> Bool.False
1445 | Addr16 -> Bool.False)
1448 | Direct -> Bool.False
1449 | Indirect -> Bool.False
1450 | Ext_indirect -> Bool.False
1451 | Registr -> Bool.False
1452 | Acc_a -> Bool.False
1453 | Acc_b -> Bool.False
1454 | Dptr -> Bool.False
1455 | Data -> Bool.False
1456 | Data16 -> Bool.False
1457 | Acc_dptr -> Bool.False
1458 | Acc_pc -> Bool.False
1459 | Ext_indirect_dptr -> Bool.False
1460 | Indirect_dptr -> Bool.False
1461 | Carry -> Bool.False
1462 | Bit_addr -> Bool.False
1463 | N_bit_addr -> Bool.False
1464 | Relative -> Bool.True
1465 | Addr11 -> Bool.False
1466 | Addr16 -> Bool.False)
1469 | Direct -> Bool.False
1470 | Indirect -> Bool.False
1471 | Ext_indirect -> Bool.False
1472 | Registr -> Bool.False
1473 | Acc_a -> Bool.False
1474 | Acc_b -> Bool.False
1475 | Dptr -> Bool.False
1476 | Data -> Bool.False
1477 | Data16 -> Bool.False
1478 | Acc_dptr -> Bool.False
1479 | Acc_pc -> Bool.False
1480 | Ext_indirect_dptr -> Bool.False
1481 | Indirect_dptr -> Bool.False
1482 | Carry -> Bool.False
1483 | Bit_addr -> Bool.False
1484 | N_bit_addr -> Bool.False
1485 | Relative -> Bool.False
1486 | Addr11 -> Bool.True
1487 | Addr16 -> Bool.False)
1490 | Direct -> Bool.False
1491 | Indirect -> Bool.False
1492 | Ext_indirect -> Bool.False
1493 | Registr -> Bool.False
1494 | Acc_a -> Bool.False
1495 | Acc_b -> Bool.False
1496 | Dptr -> Bool.False
1497 | Data -> Bool.False
1498 | Data16 -> Bool.False
1499 | Acc_dptr -> Bool.False
1500 | Acc_pc -> Bool.False
1501 | Ext_indirect_dptr -> Bool.False
1502 | Indirect_dptr -> Bool.False
1503 | Carry -> Bool.False
1504 | Bit_addr -> Bool.False
1505 | N_bit_addr -> Bool.False
1506 | Relative -> Bool.False
1507 | Addr11 -> Bool.False
1508 | Addr16 -> Bool.True)
1510 (** val is_a : addressing_mode_tag -> addressing_mode -> Bool.bool **)
1515 | DIRECT x -> Bool.True
1516 | INDIRECT x -> Bool.False
1517 | EXT_INDIRECT x -> Bool.False
1518 | REGISTER x -> Bool.False
1519 | ACC_A -> Bool.False
1520 | ACC_B -> Bool.False
1521 | DPTR -> Bool.False
1522 | DATA x -> Bool.False
1523 | DATA16 x -> Bool.False
1524 | ACC_DPTR -> Bool.False
1525 | ACC_PC -> Bool.False
1526 | EXT_INDIRECT_DPTR -> Bool.False
1527 | INDIRECT_DPTR -> Bool.False
1528 | CARRY -> Bool.False
1529 | BIT_ADDR x -> Bool.False
1530 | N_BIT_ADDR x -> Bool.False
1531 | RELATIVE x -> Bool.False
1532 | ADDR11 x -> Bool.False
1533 | ADDR16 x -> Bool.False)
1536 | DIRECT x -> Bool.False
1537 | INDIRECT x -> Bool.True
1538 | EXT_INDIRECT x -> Bool.False
1539 | REGISTER x -> Bool.False
1540 | ACC_A -> Bool.False
1541 | ACC_B -> Bool.False
1542 | DPTR -> Bool.False
1543 | DATA x -> Bool.False
1544 | DATA16 x -> Bool.False
1545 | ACC_DPTR -> Bool.False
1546 | ACC_PC -> Bool.False
1547 | EXT_INDIRECT_DPTR -> Bool.False
1548 | INDIRECT_DPTR -> Bool.False
1549 | CARRY -> Bool.False
1550 | BIT_ADDR x -> Bool.False
1551 | N_BIT_ADDR x -> Bool.False
1552 | RELATIVE x -> Bool.False
1553 | ADDR11 x -> Bool.False
1554 | ADDR16 x -> Bool.False)
1557 | DIRECT x -> Bool.False
1558 | INDIRECT x -> Bool.False
1559 | EXT_INDIRECT x -> Bool.True
1560 | REGISTER x -> Bool.False
1561 | ACC_A -> Bool.False
1562 | ACC_B -> Bool.False
1563 | DPTR -> Bool.False
1564 | DATA x -> Bool.False
1565 | DATA16 x -> Bool.False
1566 | ACC_DPTR -> Bool.False
1567 | ACC_PC -> Bool.False
1568 | EXT_INDIRECT_DPTR -> Bool.False
1569 | INDIRECT_DPTR -> Bool.False
1570 | CARRY -> Bool.False
1571 | BIT_ADDR x -> Bool.False
1572 | N_BIT_ADDR x -> Bool.False
1573 | RELATIVE x -> Bool.False
1574 | ADDR11 x -> Bool.False
1575 | ADDR16 x -> Bool.False)
1578 | DIRECT x -> Bool.False
1579 | INDIRECT x -> Bool.False
1580 | EXT_INDIRECT x -> Bool.False
1581 | REGISTER x -> Bool.True
1582 | ACC_A -> Bool.False
1583 | ACC_B -> Bool.False
1584 | DPTR -> Bool.False
1585 | DATA x -> Bool.False
1586 | DATA16 x -> Bool.False
1587 | ACC_DPTR -> Bool.False
1588 | ACC_PC -> Bool.False
1589 | EXT_INDIRECT_DPTR -> Bool.False
1590 | INDIRECT_DPTR -> Bool.False
1591 | CARRY -> Bool.False
1592 | BIT_ADDR x -> Bool.False
1593 | N_BIT_ADDR x -> Bool.False
1594 | RELATIVE x -> Bool.False
1595 | ADDR11 x -> Bool.False
1596 | ADDR16 x -> Bool.False)
1599 | DIRECT x -> Bool.False
1600 | INDIRECT x -> Bool.False
1601 | EXT_INDIRECT x -> Bool.False
1602 | REGISTER x -> Bool.False
1603 | ACC_A -> Bool.True
1604 | ACC_B -> Bool.False
1605 | DPTR -> Bool.False
1606 | DATA x -> Bool.False
1607 | DATA16 x -> Bool.False
1608 | ACC_DPTR -> Bool.False
1609 | ACC_PC -> Bool.False
1610 | EXT_INDIRECT_DPTR -> Bool.False
1611 | INDIRECT_DPTR -> Bool.False
1612 | CARRY -> Bool.False
1613 | BIT_ADDR x -> Bool.False
1614 | N_BIT_ADDR x -> Bool.False
1615 | RELATIVE x -> Bool.False
1616 | ADDR11 x -> Bool.False
1617 | ADDR16 x -> Bool.False)
1620 | DIRECT x -> Bool.False
1621 | INDIRECT x -> Bool.False
1622 | EXT_INDIRECT x -> Bool.False
1623 | REGISTER x -> Bool.False
1624 | ACC_A -> Bool.False
1625 | ACC_B -> Bool.True
1626 | DPTR -> Bool.False
1627 | DATA x -> Bool.False
1628 | DATA16 x -> Bool.False
1629 | ACC_DPTR -> Bool.False
1630 | ACC_PC -> Bool.False
1631 | EXT_INDIRECT_DPTR -> Bool.False
1632 | INDIRECT_DPTR -> Bool.False
1633 | CARRY -> Bool.False
1634 | BIT_ADDR x -> Bool.False
1635 | N_BIT_ADDR x -> Bool.False
1636 | RELATIVE x -> Bool.False
1637 | ADDR11 x -> Bool.False
1638 | ADDR16 x -> Bool.False)
1641 | DIRECT x -> Bool.False
1642 | INDIRECT x -> Bool.False
1643 | EXT_INDIRECT x -> Bool.False
1644 | REGISTER x -> Bool.False
1645 | ACC_A -> Bool.False
1646 | ACC_B -> Bool.False
1648 | DATA x -> Bool.False
1649 | DATA16 x -> Bool.False
1650 | ACC_DPTR -> Bool.False
1651 | ACC_PC -> Bool.False
1652 | EXT_INDIRECT_DPTR -> Bool.False
1653 | INDIRECT_DPTR -> Bool.False
1654 | CARRY -> Bool.False
1655 | BIT_ADDR x -> Bool.False
1656 | N_BIT_ADDR x -> Bool.False
1657 | RELATIVE x -> Bool.False
1658 | ADDR11 x -> Bool.False
1659 | ADDR16 x -> Bool.False)
1662 | DIRECT x -> Bool.False
1663 | INDIRECT x -> Bool.False
1664 | EXT_INDIRECT x -> Bool.False
1665 | REGISTER x -> Bool.False
1666 | ACC_A -> Bool.False
1667 | ACC_B -> Bool.False
1668 | DPTR -> Bool.False
1669 | DATA x -> Bool.True
1670 | DATA16 x -> Bool.False
1671 | ACC_DPTR -> Bool.False
1672 | ACC_PC -> Bool.False
1673 | EXT_INDIRECT_DPTR -> Bool.False
1674 | INDIRECT_DPTR -> Bool.False
1675 | CARRY -> Bool.False
1676 | BIT_ADDR x -> Bool.False
1677 | N_BIT_ADDR x -> Bool.False
1678 | RELATIVE x -> Bool.False
1679 | ADDR11 x -> Bool.False
1680 | ADDR16 x -> Bool.False)
1683 | DIRECT x -> Bool.False
1684 | INDIRECT x -> Bool.False
1685 | EXT_INDIRECT x -> Bool.False
1686 | REGISTER x -> Bool.False
1687 | ACC_A -> Bool.False
1688 | ACC_B -> Bool.False
1689 | DPTR -> Bool.False
1690 | DATA x -> Bool.False
1691 | DATA16 x -> Bool.True
1692 | ACC_DPTR -> Bool.False
1693 | ACC_PC -> Bool.False
1694 | EXT_INDIRECT_DPTR -> Bool.False
1695 | INDIRECT_DPTR -> Bool.False
1696 | CARRY -> Bool.False
1697 | BIT_ADDR x -> Bool.False
1698 | N_BIT_ADDR x -> Bool.False
1699 | RELATIVE x -> Bool.False
1700 | ADDR11 x -> Bool.False
1701 | ADDR16 x -> Bool.False)
1704 | DIRECT x -> Bool.False
1705 | INDIRECT x -> Bool.False
1706 | EXT_INDIRECT x -> Bool.False
1707 | REGISTER x -> Bool.False
1708 | ACC_A -> Bool.False
1709 | ACC_B -> Bool.False
1710 | DPTR -> Bool.False
1711 | DATA x -> Bool.False
1712 | DATA16 x -> Bool.False
1713 | ACC_DPTR -> Bool.True
1714 | ACC_PC -> Bool.False
1715 | EXT_INDIRECT_DPTR -> Bool.False
1716 | INDIRECT_DPTR -> Bool.False
1717 | CARRY -> Bool.False
1718 | BIT_ADDR x -> Bool.False
1719 | N_BIT_ADDR x -> Bool.False
1720 | RELATIVE x -> Bool.False
1721 | ADDR11 x -> Bool.False
1722 | ADDR16 x -> Bool.False)
1725 | DIRECT x -> Bool.False
1726 | INDIRECT x -> Bool.False
1727 | EXT_INDIRECT x -> Bool.False
1728 | REGISTER x -> Bool.False
1729 | ACC_A -> Bool.False
1730 | ACC_B -> Bool.False
1731 | DPTR -> Bool.False
1732 | DATA x -> Bool.False
1733 | DATA16 x -> Bool.False
1734 | ACC_DPTR -> Bool.False
1735 | ACC_PC -> Bool.True
1736 | EXT_INDIRECT_DPTR -> Bool.False
1737 | INDIRECT_DPTR -> Bool.False
1738 | CARRY -> Bool.False
1739 | BIT_ADDR x -> Bool.False
1740 | N_BIT_ADDR x -> Bool.False
1741 | RELATIVE x -> Bool.False
1742 | ADDR11 x -> Bool.False
1743 | ADDR16 x -> Bool.False)
1744 | Ext_indirect_dptr ->
1746 | DIRECT x -> Bool.False
1747 | INDIRECT x -> Bool.False
1748 | EXT_INDIRECT x -> Bool.False
1749 | REGISTER x -> Bool.False
1750 | ACC_A -> Bool.False
1751 | ACC_B -> Bool.False
1752 | DPTR -> Bool.False
1753 | DATA x -> Bool.False
1754 | DATA16 x -> Bool.False
1755 | ACC_DPTR -> Bool.False
1756 | ACC_PC -> Bool.False
1757 | EXT_INDIRECT_DPTR -> Bool.True
1758 | INDIRECT_DPTR -> Bool.False
1759 | CARRY -> Bool.False
1760 | BIT_ADDR x -> Bool.False
1761 | N_BIT_ADDR x -> Bool.False
1762 | RELATIVE x -> Bool.False
1763 | ADDR11 x -> Bool.False
1764 | ADDR16 x -> Bool.False)
1767 | DIRECT x -> Bool.False
1768 | INDIRECT x -> Bool.False
1769 | EXT_INDIRECT x -> Bool.False
1770 | REGISTER x -> Bool.False
1771 | ACC_A -> Bool.False
1772 | ACC_B -> Bool.False
1773 | DPTR -> Bool.False
1774 | DATA x -> Bool.False
1775 | DATA16 x -> Bool.False
1776 | ACC_DPTR -> Bool.False
1777 | ACC_PC -> Bool.False
1778 | EXT_INDIRECT_DPTR -> Bool.False
1779 | INDIRECT_DPTR -> Bool.True
1780 | CARRY -> Bool.False
1781 | BIT_ADDR x -> Bool.False
1782 | N_BIT_ADDR x -> Bool.False
1783 | RELATIVE x -> Bool.False
1784 | ADDR11 x -> Bool.False
1785 | ADDR16 x -> Bool.False)
1788 | DIRECT x -> Bool.False
1789 | INDIRECT x -> Bool.False
1790 | EXT_INDIRECT x -> Bool.False
1791 | REGISTER x -> Bool.False
1792 | ACC_A -> Bool.False
1793 | ACC_B -> Bool.False
1794 | DPTR -> Bool.False
1795 | DATA x -> Bool.False
1796 | DATA16 x -> Bool.False
1797 | ACC_DPTR -> Bool.False
1798 | ACC_PC -> Bool.False
1799 | EXT_INDIRECT_DPTR -> Bool.False
1800 | INDIRECT_DPTR -> Bool.False
1801 | CARRY -> Bool.True
1802 | BIT_ADDR x -> Bool.False
1803 | N_BIT_ADDR x -> Bool.False
1804 | RELATIVE x -> Bool.False
1805 | ADDR11 x -> Bool.False
1806 | ADDR16 x -> Bool.False)
1809 | DIRECT x -> Bool.False
1810 | INDIRECT x -> Bool.False
1811 | EXT_INDIRECT x -> Bool.False
1812 | REGISTER x -> Bool.False
1813 | ACC_A -> Bool.False
1814 | ACC_B -> Bool.False
1815 | DPTR -> Bool.False
1816 | DATA x -> Bool.False
1817 | DATA16 x -> Bool.False
1818 | ACC_DPTR -> Bool.False
1819 | ACC_PC -> Bool.False
1820 | EXT_INDIRECT_DPTR -> Bool.False
1821 | INDIRECT_DPTR -> Bool.False
1822 | CARRY -> Bool.False
1823 | BIT_ADDR x -> Bool.True
1824 | N_BIT_ADDR x -> Bool.False
1825 | RELATIVE x -> Bool.False
1826 | ADDR11 x -> Bool.False
1827 | ADDR16 x -> Bool.False)
1830 | DIRECT x -> Bool.False
1831 | INDIRECT x -> Bool.False
1832 | EXT_INDIRECT x -> Bool.False
1833 | REGISTER x -> Bool.False
1834 | ACC_A -> Bool.False
1835 | ACC_B -> Bool.False
1836 | DPTR -> Bool.False
1837 | DATA x -> Bool.False
1838 | DATA16 x -> Bool.False
1839 | ACC_DPTR -> Bool.False
1840 | ACC_PC -> Bool.False
1841 | EXT_INDIRECT_DPTR -> Bool.False
1842 | INDIRECT_DPTR -> Bool.False
1843 | CARRY -> Bool.False
1844 | BIT_ADDR x -> Bool.False
1845 | N_BIT_ADDR x -> Bool.True
1846 | RELATIVE x -> Bool.False
1847 | ADDR11 x -> Bool.False
1848 | ADDR16 x -> Bool.False)
1851 | DIRECT x -> Bool.False
1852 | INDIRECT x -> Bool.False
1853 | EXT_INDIRECT x -> Bool.False
1854 | REGISTER x -> Bool.False
1855 | ACC_A -> Bool.False
1856 | ACC_B -> Bool.False
1857 | DPTR -> Bool.False
1858 | DATA x -> Bool.False
1859 | DATA16 x -> Bool.False
1860 | ACC_DPTR -> Bool.False
1861 | ACC_PC -> Bool.False
1862 | EXT_INDIRECT_DPTR -> Bool.False
1863 | INDIRECT_DPTR -> Bool.False
1864 | CARRY -> Bool.False
1865 | BIT_ADDR x -> Bool.False
1866 | N_BIT_ADDR x -> Bool.False
1867 | RELATIVE x -> Bool.True
1868 | ADDR11 x -> Bool.False
1869 | ADDR16 x -> Bool.False)
1872 | DIRECT x -> Bool.False
1873 | INDIRECT x -> Bool.False
1874 | EXT_INDIRECT x -> Bool.False
1875 | REGISTER x -> Bool.False
1876 | ACC_A -> Bool.False
1877 | ACC_B -> Bool.False
1878 | DPTR -> Bool.False
1879 | DATA x -> Bool.False
1880 | DATA16 x -> Bool.False
1881 | ACC_DPTR -> Bool.False
1882 | ACC_PC -> Bool.False
1883 | EXT_INDIRECT_DPTR -> Bool.False
1884 | INDIRECT_DPTR -> Bool.False
1885 | CARRY -> Bool.False
1886 | BIT_ADDR x -> Bool.False
1887 | N_BIT_ADDR x -> Bool.False
1888 | RELATIVE x -> Bool.False
1889 | ADDR11 x -> Bool.True
1890 | ADDR16 x -> Bool.False)
1893 | DIRECT x -> Bool.False
1894 | INDIRECT x -> Bool.False
1895 | EXT_INDIRECT x -> Bool.False
1896 | REGISTER x -> Bool.False
1897 | ACC_A -> Bool.False
1898 | ACC_B -> Bool.False
1899 | DPTR -> Bool.False
1900 | DATA x -> Bool.False
1901 | DATA16 x -> Bool.False
1902 | ACC_DPTR -> Bool.False
1903 | ACC_PC -> Bool.False
1904 | EXT_INDIRECT_DPTR -> Bool.False
1905 | INDIRECT_DPTR -> Bool.False
1906 | CARRY -> Bool.False
1907 | BIT_ADDR x -> Bool.False
1908 | N_BIT_ADDR x -> Bool.False
1909 | RELATIVE x -> Bool.False
1910 | ADDR11 x -> Bool.False
1911 | ADDR16 x -> Bool.True)
1914 Nat.nat -> addressing_mode_tag Vector.vector -> addressing_mode ->
1916 let rec is_in n l a =
1918 | Vector.VEmpty -> Bool.False
1919 | Vector.VCons (m, he, tl) -> Bool.orb (is_a he a) (is_in m tl a)
1921 type subaddressing_mode =
1923 (* singleton inductive, whose constructor was mk_subaddressing_mode *)
1925 (** val subaddressing_mode_rect_Type4 :
1926 Nat.nat -> addressing_mode_tag Vector.vector -> (addressing_mode -> __ ->
1927 'a1) -> subaddressing_mode -> 'a1 **)
1928 let rec subaddressing_mode_rect_Type4 n l h_mk_subaddressing_mode x_666 =
1929 let subaddressing_modeel = x_666 in
1930 h_mk_subaddressing_mode subaddressing_modeel __
1932 (** val subaddressing_mode_rect_Type5 :
1933 Nat.nat -> addressing_mode_tag Vector.vector -> (addressing_mode -> __ ->
1934 'a1) -> subaddressing_mode -> 'a1 **)
1935 let rec subaddressing_mode_rect_Type5 n l h_mk_subaddressing_mode x_668 =
1936 let subaddressing_modeel = x_668 in
1937 h_mk_subaddressing_mode subaddressing_modeel __
1939 (** val subaddressing_mode_rect_Type3 :
1940 Nat.nat -> addressing_mode_tag Vector.vector -> (addressing_mode -> __ ->
1941 'a1) -> subaddressing_mode -> 'a1 **)
1942 let rec subaddressing_mode_rect_Type3 n l h_mk_subaddressing_mode x_670 =
1943 let subaddressing_modeel = x_670 in
1944 h_mk_subaddressing_mode subaddressing_modeel __
1946 (** val subaddressing_mode_rect_Type2 :
1947 Nat.nat -> addressing_mode_tag Vector.vector -> (addressing_mode -> __ ->
1948 'a1) -> subaddressing_mode -> 'a1 **)
1949 let rec subaddressing_mode_rect_Type2 n l h_mk_subaddressing_mode x_672 =
1950 let subaddressing_modeel = x_672 in
1951 h_mk_subaddressing_mode subaddressing_modeel __
1953 (** val subaddressing_mode_rect_Type1 :
1954 Nat.nat -> addressing_mode_tag Vector.vector -> (addressing_mode -> __ ->
1955 'a1) -> subaddressing_mode -> 'a1 **)
1956 let rec subaddressing_mode_rect_Type1 n l h_mk_subaddressing_mode x_674 =
1957 let subaddressing_modeel = x_674 in
1958 h_mk_subaddressing_mode subaddressing_modeel __
1960 (** val subaddressing_mode_rect_Type0 :
1961 Nat.nat -> addressing_mode_tag Vector.vector -> (addressing_mode -> __ ->
1962 'a1) -> subaddressing_mode -> 'a1 **)
1963 let rec subaddressing_mode_rect_Type0 n l h_mk_subaddressing_mode x_676 =
1964 let subaddressing_modeel = x_676 in
1965 h_mk_subaddressing_mode subaddressing_modeel __
1967 (** val subaddressing_modeel :
1968 Nat.nat -> addressing_mode_tag Vector.vector -> subaddressing_mode ->
1970 let rec subaddressing_modeel n l xxx =
1971 let yyy = xxx in yyy
1973 (** val subaddressing_mode_inv_rect_Type4 :
1974 Nat.nat -> addressing_mode_tag Vector.vector -> subaddressing_mode ->
1975 (addressing_mode -> __ -> __ -> 'a1) -> 'a1 **)
1976 let subaddressing_mode_inv_rect_Type4 x1 x2 hterm h1 =
1977 let hcut = subaddressing_mode_rect_Type4 x1 x2 h1 hterm in hcut __
1979 (** val subaddressing_mode_inv_rect_Type3 :
1980 Nat.nat -> addressing_mode_tag Vector.vector -> subaddressing_mode ->
1981 (addressing_mode -> __ -> __ -> 'a1) -> 'a1 **)
1982 let subaddressing_mode_inv_rect_Type3 x1 x2 hterm h1 =
1983 let hcut = subaddressing_mode_rect_Type3 x1 x2 h1 hterm in hcut __
1985 (** val subaddressing_mode_inv_rect_Type2 :
1986 Nat.nat -> addressing_mode_tag Vector.vector -> subaddressing_mode ->
1987 (addressing_mode -> __ -> __ -> 'a1) -> 'a1 **)
1988 let subaddressing_mode_inv_rect_Type2 x1 x2 hterm h1 =
1989 let hcut = subaddressing_mode_rect_Type2 x1 x2 h1 hterm in hcut __
1991 (** val subaddressing_mode_inv_rect_Type1 :
1992 Nat.nat -> addressing_mode_tag Vector.vector -> subaddressing_mode ->
1993 (addressing_mode -> __ -> __ -> 'a1) -> 'a1 **)
1994 let subaddressing_mode_inv_rect_Type1 x1 x2 hterm h1 =
1995 let hcut = subaddressing_mode_rect_Type1 x1 x2 h1 hterm in hcut __
1997 (** val subaddressing_mode_inv_rect_Type0 :
1998 Nat.nat -> addressing_mode_tag Vector.vector -> subaddressing_mode ->
1999 (addressing_mode -> __ -> __ -> 'a1) -> 'a1 **)
2000 let subaddressing_mode_inv_rect_Type0 x1 x2 hterm h1 =
2001 let hcut = subaddressing_mode_rect_Type0 x1 x2 h1 hterm in hcut __
2003 (** val subaddressing_mode_discr :
2004 Nat.nat -> addressing_mode_tag Vector.vector -> subaddressing_mode ->
2005 subaddressing_mode -> __ **)
2006 let subaddressing_mode_discr a1 a2 x y =
2007 Logic.eq_rect_Type2 x (let a0 = x in Obj.magic (fun _ dH -> dH __ __)) y
2009 (** val subaddressing_mode_jmdiscr :
2010 Nat.nat -> addressing_mode_tag Vector.vector -> subaddressing_mode ->
2011 subaddressing_mode -> __ **)
2012 let subaddressing_mode_jmdiscr a1 a2 x y =
2013 Logic.eq_rect_Type2 x (let a0 = x in Obj.magic (fun _ dH -> dH __ __)) y
2015 (** val dpi1__o__subaddressing_modeel__o__inject :
2016 Nat.nat -> addressing_mode_tag Vector.vector -> (subaddressing_mode, 'a1)
2017 Types.dPair -> addressing_mode Types.sig0 **)
2018 let dpi1__o__subaddressing_modeel__o__inject x1 x2 x4 =
2019 subaddressing_modeel x1 x2 x4.Types.dpi1
2021 (** val eject__o__subaddressing_modeel__o__inject :
2022 Nat.nat -> addressing_mode_tag Vector.vector -> subaddressing_mode
2023 Types.sig0 -> addressing_mode Types.sig0 **)
2024 let eject__o__subaddressing_modeel__o__inject x1 x2 x4 =
2025 subaddressing_modeel x1 x2 (Types.pi1 x4)
2027 (** val subaddressing_modeel__o__inject :
2028 Nat.nat -> addressing_mode_tag Vector.vector -> subaddressing_mode ->
2029 addressing_mode Types.sig0 **)
2030 let subaddressing_modeel__o__inject x1 x2 x3 =
2031 subaddressing_modeel x1 x2 x3
2033 (** val dpi1__o__subaddressing_modeel :
2034 Nat.nat -> addressing_mode_tag Vector.vector -> (subaddressing_mode, 'a1)
2035 Types.dPair -> addressing_mode **)
2036 let dpi1__o__subaddressing_modeel x0 x1 x3 =
2037 subaddressing_modeel x0 x1 x3.Types.dpi1
2039 (** val eject__o__subaddressing_modeel :
2040 Nat.nat -> addressing_mode_tag Vector.vector -> subaddressing_mode
2041 Types.sig0 -> addressing_mode **)
2042 let eject__o__subaddressing_modeel x0 x1 x3 =
2043 subaddressing_modeel x0 x1 (Types.pi1 x3)
2045 type 'x1 dpi1__o__subaddressing_mode = subaddressing_mode
2047 type eject__o__subaddressing_mode = subaddressing_mode
2049 (** val dpi1__o__subaddressing_modeel__o__mk_subaddressing_mode__o__inject :
2050 Nat.nat -> Nat.nat -> addressing_mode_tag Vector.vector ->
2051 addressing_mode_tag Vector.vector -> (subaddressing_mode, 'a1)
2052 Types.dPair -> subaddressing_mode Types.sig0 **)
2053 let dpi1__o__subaddressing_modeel__o__mk_subaddressing_mode__o__inject x0 x1 x2 x3 x6 =
2054 dpi1__o__subaddressing_modeel x0 x2 x6
2056 (** val dpi1__o__subaddressing_modeel__o__mk_subaddressing_mode__o__subaddressing_modeel__o__inject :
2057 Nat.nat -> Nat.nat -> addressing_mode_tag Vector.vector ->
2058 addressing_mode_tag Vector.vector -> (subaddressing_mode, 'a1)
2059 Types.dPair -> addressing_mode Types.sig0 **)
2060 let dpi1__o__subaddressing_modeel__o__mk_subaddressing_mode__o__subaddressing_modeel__o__inject x0 x2 x3 x4 x6 =
2061 subaddressing_modeel__o__inject x2 x4
2062 (dpi1__o__subaddressing_modeel x0 x3 x6)
2064 (** val dpi1__o__subaddressing_modeel__o__mk_subaddressing_mode__o__subaddressing_modeel :
2065 Nat.nat -> Nat.nat -> addressing_mode_tag Vector.vector ->
2066 addressing_mode_tag Vector.vector -> (subaddressing_mode, 'a1)
2067 Types.dPair -> addressing_mode **)
2068 let dpi1__o__subaddressing_modeel__o__mk_subaddressing_mode__o__subaddressing_modeel x0 x1 x2 x3 x5 =
2069 subaddressing_modeel x1 x3 (dpi1__o__subaddressing_modeel x0 x2 x5)
2071 (** val eject__o__subaddressing_modeel__o__mk_subaddressing_mode__o__inject :
2072 Nat.nat -> Nat.nat -> addressing_mode_tag Vector.vector ->
2073 addressing_mode_tag Vector.vector -> subaddressing_mode Types.sig0 ->
2074 subaddressing_mode Types.sig0 **)
2075 let eject__o__subaddressing_modeel__o__mk_subaddressing_mode__o__inject x0 x1 x2 x3 x6 =
2076 eject__o__subaddressing_modeel x0 x2 x6
2078 (** val eject__o__subaddressing_modeel__o__mk_subaddressing_mode__o__subaddressing_modeel__o__inject :
2079 Nat.nat -> Nat.nat -> addressing_mode_tag Vector.vector ->
2080 addressing_mode_tag Vector.vector -> subaddressing_mode Types.sig0 ->
2081 addressing_mode Types.sig0 **)
2082 let eject__o__subaddressing_modeel__o__mk_subaddressing_mode__o__subaddressing_modeel__o__inject x0 x2 x3 x4 x6 =
2083 subaddressing_modeel__o__inject x2 x4
2084 (eject__o__subaddressing_modeel x0 x3 x6)
2086 (** val eject__o__subaddressing_modeel__o__mk_subaddressing_mode__o__subaddressing_modeel :
2087 Nat.nat -> Nat.nat -> addressing_mode_tag Vector.vector ->
2088 addressing_mode_tag Vector.vector -> subaddressing_mode Types.sig0 ->
2090 let eject__o__subaddressing_modeel__o__mk_subaddressing_mode__o__subaddressing_modeel x0 x1 x2 x3 x5 =
2091 subaddressing_modeel x1 x3 (eject__o__subaddressing_modeel x0 x2 x5)
2093 (** val subaddressing_modeel__o__mk_subaddressing_mode__o__inject :
2094 Nat.nat -> Nat.nat -> addressing_mode_tag Vector.vector ->
2095 addressing_mode_tag Vector.vector -> subaddressing_mode ->
2096 subaddressing_mode Types.sig0 **)
2097 let subaddressing_modeel__o__mk_subaddressing_mode__o__inject x0 x1 x2 x3 x4 =
2098 subaddressing_modeel x0 x2 x4
2100 (** val subaddressing_modeel__o__mk_subaddressing_mode__o__subaddressing_modeel__o__inject :
2101 Nat.nat -> Nat.nat -> addressing_mode_tag Vector.vector ->
2102 addressing_mode_tag Vector.vector -> subaddressing_mode ->
2103 addressing_mode Types.sig0 **)
2104 let subaddressing_modeel__o__mk_subaddressing_mode__o__subaddressing_modeel__o__inject x0 x2 x3 x4 x5 =
2105 subaddressing_modeel__o__inject x2 x4 (subaddressing_modeel x0 x3 x5)
2107 (** val subaddressing_modeel__o__mk_subaddressing_mode__o__subaddressing_modeel :
2108 Nat.nat -> Nat.nat -> addressing_mode_tag Vector.vector ->
2109 addressing_mode_tag Vector.vector -> subaddressing_mode ->
2111 let subaddressing_modeel__o__mk_subaddressing_mode__o__subaddressing_modeel x0 x1 x2 x3 x4 =
2112 subaddressing_modeel x1 x3 (subaddressing_modeel x0 x2 x4)
2114 (** val dpi1__o__mk_subaddressing_mode__o__inject :
2115 Nat.nat -> (addressing_mode, 'a1) Types.dPair -> addressing_mode_tag
2116 Vector.vector -> subaddressing_mode Types.sig0 **)
2117 let dpi1__o__mk_subaddressing_mode__o__inject x1 x2 x3 =
2120 (** val dpi1__o__mk_subaddressing_mode__o__subaddressing_modeel__o__inject :
2121 Nat.nat -> (addressing_mode, 'a1) Types.dPair -> addressing_mode_tag
2122 Vector.vector -> addressing_mode Types.sig0 **)
2123 let dpi1__o__mk_subaddressing_mode__o__subaddressing_modeel__o__inject x2 x3 x4 =
2124 subaddressing_modeel__o__inject x2 x4 x3.Types.dpi1
2126 (** val dpi1__o__mk_subaddressing_mode__o__subaddressing_modeel :
2127 Nat.nat -> (addressing_mode, 'a1) Types.dPair -> addressing_mode_tag
2128 Vector.vector -> addressing_mode **)
2129 let dpi1__o__mk_subaddressing_mode__o__subaddressing_modeel x1 x2 x3 =
2130 subaddressing_modeel x1 x3 x2.Types.dpi1
2132 (** val eject__o__mk_subaddressing_mode__o__inject :
2133 Nat.nat -> addressing_mode Types.sig0 -> addressing_mode_tag
2134 Vector.vector -> subaddressing_mode Types.sig0 **)
2135 let eject__o__mk_subaddressing_mode__o__inject x1 x2 x3 =
2138 (** val eject__o__mk_subaddressing_mode__o__subaddressing_modeel__o__inject :
2139 Nat.nat -> addressing_mode Types.sig0 -> addressing_mode_tag
2140 Vector.vector -> addressing_mode Types.sig0 **)
2141 let eject__o__mk_subaddressing_mode__o__subaddressing_modeel__o__inject x2 x3 x4 =
2142 subaddressing_modeel__o__inject x2 x4 (Types.pi1 x3)
2144 (** val eject__o__mk_subaddressing_mode__o__subaddressing_modeel :
2145 Nat.nat -> addressing_mode Types.sig0 -> addressing_mode_tag
2146 Vector.vector -> addressing_mode **)
2147 let eject__o__mk_subaddressing_mode__o__subaddressing_modeel x1 x2 x3 =
2148 subaddressing_modeel x1 x3 (Types.pi1 x2)
2150 (** val mk_subaddressing_mode__o__subaddressing_modeel :
2151 Nat.nat -> addressing_mode -> addressing_mode_tag Vector.vector ->
2153 let mk_subaddressing_mode__o__subaddressing_modeel x0 x1 x2 =
2154 subaddressing_modeel x0 x2 x1
2156 (** val mk_subaddressing_mode__o__subaddressing_modeel__o__inject :
2157 Nat.nat -> addressing_mode -> addressing_mode_tag Vector.vector ->
2158 addressing_mode Types.sig0 **)
2159 let mk_subaddressing_mode__o__subaddressing_modeel__o__inject x1 x2 x3 =
2160 subaddressing_modeel__o__inject x1 x3 x2
2162 (** val mk_subaddressing_mode__o__inject :
2163 Nat.nat -> addressing_mode -> addressing_mode_tag Vector.vector ->
2164 subaddressing_mode Types.sig0 **)
2165 let mk_subaddressing_mode__o__inject x0 x1 x2 =
2168 (** val dpi1__o__subaddressing_modeel__o__mk_subaddressing_mode :
2169 Nat.nat -> Nat.nat -> addressing_mode_tag Vector.vector ->
2170 addressing_mode_tag Vector.vector -> (subaddressing_mode, 'a1)
2171 Types.dPair -> subaddressing_mode **)
2172 let dpi1__o__subaddressing_modeel__o__mk_subaddressing_mode x0 x1 x2 x3 x5 =
2173 dpi1__o__subaddressing_modeel x0 x2 x5
2175 (** val eject__o__subaddressing_modeel__o__mk_subaddressing_mode :
2176 Nat.nat -> Nat.nat -> addressing_mode_tag Vector.vector ->
2177 addressing_mode_tag Vector.vector -> subaddressing_mode Types.sig0 ->
2178 subaddressing_mode **)
2179 let eject__o__subaddressing_modeel__o__mk_subaddressing_mode x0 x1 x2 x3 x5 =
2180 eject__o__subaddressing_modeel x0 x2 x5
2182 (** val subaddressing_modeel__o__mk_subaddressing_mode :
2183 Nat.nat -> Nat.nat -> addressing_mode_tag Vector.vector ->
2184 addressing_mode_tag Vector.vector -> subaddressing_mode ->
2185 subaddressing_mode **)
2186 let subaddressing_modeel__o__mk_subaddressing_mode x0 x1 x2 x3 x4 =
2187 subaddressing_modeel x0 x2 x4
2189 (** val dpi1__o__mk_subaddressing_mode :
2190 Nat.nat -> (addressing_mode, 'a1) Types.dPair -> addressing_mode_tag
2191 Vector.vector -> subaddressing_mode **)
2192 let dpi1__o__mk_subaddressing_mode x1 x2 x3 =
2195 (** val eject__o__mk_subaddressing_mode :
2196 Nat.nat -> addressing_mode Types.sig0 -> addressing_mode_tag
2197 Vector.vector -> subaddressing_mode **)
2198 let eject__o__mk_subaddressing_mode x1 x2 x3 =
2201 type 'a preinstruction =
2202 | ADD of subaddressing_mode * subaddressing_mode
2203 | ADDC of subaddressing_mode * subaddressing_mode
2204 | SUBB of subaddressing_mode * subaddressing_mode
2205 | INC of subaddressing_mode
2206 | DEC of subaddressing_mode
2207 | MUL of subaddressing_mode * subaddressing_mode
2208 | DIV of subaddressing_mode * subaddressing_mode
2209 | DA of subaddressing_mode
2212 | JB of subaddressing_mode * 'a
2213 | JNB of subaddressing_mode * 'a
2214 | JBC of subaddressing_mode * 'a
2217 | CJNE of ((subaddressing_mode, subaddressing_mode) Types.prod,
2218 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum *
2220 | DJNZ of subaddressing_mode * 'a
2221 | ANL of (((subaddressing_mode, subaddressing_mode) Types.prod,
2222 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2223 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum
2224 | ORL of (((subaddressing_mode, subaddressing_mode) Types.prod,
2225 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2226 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum
2227 | XRL of ((subaddressing_mode, subaddressing_mode) Types.prod,
2228 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum
2229 | CLR of subaddressing_mode
2230 | CPL of subaddressing_mode
2231 | RL of subaddressing_mode
2232 | RLC of subaddressing_mode
2233 | RR of subaddressing_mode
2234 | RRC of subaddressing_mode
2235 | SWAP of subaddressing_mode
2236 | MOV of ((((((subaddressing_mode, subaddressing_mode) Types.prod,
2237 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2238 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2239 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2240 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2241 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum
2242 | MOVX of ((subaddressing_mode, subaddressing_mode) Types.prod,
2243 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum
2244 | SETB of subaddressing_mode
2245 | PUSH of subaddressing_mode
2246 | POP of subaddressing_mode
2247 | XCH of subaddressing_mode * subaddressing_mode
2248 | XCHD of subaddressing_mode * subaddressing_mode
2252 | JMP of subaddressing_mode
2254 (** val preinstruction_rect_Type4 :
2255 (subaddressing_mode -> subaddressing_mode -> 'a2) -> (subaddressing_mode
2256 -> subaddressing_mode -> 'a2) -> (subaddressing_mode ->
2257 subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2258 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> subaddressing_mode
2259 -> 'a2) -> (subaddressing_mode -> subaddressing_mode -> 'a2) ->
2260 (subaddressing_mode -> 'a2) -> ('a1 -> 'a2) -> ('a1 -> 'a2) ->
2261 (subaddressing_mode -> 'a1 -> 'a2) -> (subaddressing_mode -> 'a1 -> 'a2)
2262 -> (subaddressing_mode -> 'a1 -> 'a2) -> ('a1 -> 'a2) -> ('a1 -> 'a2) ->
2263 (((subaddressing_mode, subaddressing_mode) Types.prod,
2264 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> 'a1 ->
2265 'a2) -> (subaddressing_mode -> 'a1 -> 'a2) -> ((((subaddressing_mode,
2266 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2267 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2268 Types.prod) Types.sum -> 'a2) -> ((((subaddressing_mode,
2269 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2270 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2271 Types.prod) Types.sum -> 'a2) -> (((subaddressing_mode,
2272 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2273 Types.prod) Types.sum -> 'a2) -> (subaddressing_mode -> 'a2) ->
2274 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2275 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2276 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2277 (((((((subaddressing_mode, subaddressing_mode) Types.prod,
2278 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2279 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2280 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2281 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2282 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> 'a2) ->
2283 (((subaddressing_mode, subaddressing_mode) Types.prod,
2284 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> 'a2) ->
2285 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2286 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> subaddressing_mode
2287 -> 'a2) -> (subaddressing_mode -> subaddressing_mode -> 'a2) -> 'a2 ->
2288 'a2 -> 'a2 -> (subaddressing_mode -> 'a2) -> 'a1 preinstruction -> 'a2 **)
2289 let rec preinstruction_rect_Type4 h_ADD h_ADDC h_SUBB h_INC h_DEC h_MUL h_DIV h_DA h_JC h_JNC h_JB h_JNB h_JBC h_JZ h_JNZ h_CJNE h_DJNZ h_ANL h_ORL h_XRL h_CLR h_CPL h_RL h_RLC h_RR h_RRC h_SWAP h_MOV h_MOVX h_SETB h_PUSH h_POP h_XCH h_XCHD h_RET h_RETI h_NOP h_JMP = function
2290 | ADD (x_778, x_777) -> h_ADD x_778 x_777
2291 | ADDC (x_780, x_779) -> h_ADDC x_780 x_779
2292 | SUBB (x_782, x_781) -> h_SUBB x_782 x_781
2293 | INC x_783 -> h_INC x_783
2294 | DEC x_784 -> h_DEC x_784
2295 | MUL (x_786, x_785) -> h_MUL x_786 x_785
2296 | DIV (x_788, x_787) -> h_DIV x_788 x_787
2297 | DA x_789 -> h_DA x_789
2298 | JC x_790 -> h_JC x_790
2299 | JNC x_791 -> h_JNC x_791
2300 | JB (x_793, x_792) -> h_JB x_793 x_792
2301 | JNB (x_795, x_794) -> h_JNB x_795 x_794
2302 | JBC (x_797, x_796) -> h_JBC x_797 x_796
2303 | JZ x_798 -> h_JZ x_798
2304 | JNZ x_799 -> h_JNZ x_799
2305 | CJNE (x_801, x_800) -> h_CJNE x_801 x_800
2306 | DJNZ (x_803, x_802) -> h_DJNZ x_803 x_802
2307 | ANL x_804 -> h_ANL x_804
2308 | ORL x_805 -> h_ORL x_805
2309 | XRL x_806 -> h_XRL x_806
2310 | CLR x_807 -> h_CLR x_807
2311 | CPL x_808 -> h_CPL x_808
2312 | RL x_809 -> h_RL x_809
2313 | RLC x_810 -> h_RLC x_810
2314 | RR x_811 -> h_RR x_811
2315 | RRC x_812 -> h_RRC x_812
2316 | SWAP x_813 -> h_SWAP x_813
2317 | MOV x_814 -> h_MOV x_814
2318 | MOVX x_815 -> h_MOVX x_815
2319 | SETB x_816 -> h_SETB x_816
2320 | PUSH x_817 -> h_PUSH x_817
2321 | POP x_818 -> h_POP x_818
2322 | XCH (x_820, x_819) -> h_XCH x_820 x_819
2323 | XCHD (x_822, x_821) -> h_XCHD x_822 x_821
2327 | JMP x_823 -> h_JMP x_823
2329 (** val preinstruction_rect_Type5 :
2330 (subaddressing_mode -> subaddressing_mode -> 'a2) -> (subaddressing_mode
2331 -> subaddressing_mode -> 'a2) -> (subaddressing_mode ->
2332 subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2333 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> subaddressing_mode
2334 -> 'a2) -> (subaddressing_mode -> subaddressing_mode -> 'a2) ->
2335 (subaddressing_mode -> 'a2) -> ('a1 -> 'a2) -> ('a1 -> 'a2) ->
2336 (subaddressing_mode -> 'a1 -> 'a2) -> (subaddressing_mode -> 'a1 -> 'a2)
2337 -> (subaddressing_mode -> 'a1 -> 'a2) -> ('a1 -> 'a2) -> ('a1 -> 'a2) ->
2338 (((subaddressing_mode, subaddressing_mode) Types.prod,
2339 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> 'a1 ->
2340 'a2) -> (subaddressing_mode -> 'a1 -> 'a2) -> ((((subaddressing_mode,
2341 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2342 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2343 Types.prod) Types.sum -> 'a2) -> ((((subaddressing_mode,
2344 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2345 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2346 Types.prod) Types.sum -> 'a2) -> (((subaddressing_mode,
2347 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2348 Types.prod) Types.sum -> 'a2) -> (subaddressing_mode -> 'a2) ->
2349 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2350 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2351 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2352 (((((((subaddressing_mode, subaddressing_mode) Types.prod,
2353 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2354 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2355 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2356 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2357 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> 'a2) ->
2358 (((subaddressing_mode, subaddressing_mode) Types.prod,
2359 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> 'a2) ->
2360 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2361 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> subaddressing_mode
2362 -> 'a2) -> (subaddressing_mode -> subaddressing_mode -> 'a2) -> 'a2 ->
2363 'a2 -> 'a2 -> (subaddressing_mode -> 'a2) -> 'a1 preinstruction -> 'a2 **)
2364 let rec preinstruction_rect_Type5 h_ADD h_ADDC h_SUBB h_INC h_DEC h_MUL h_DIV h_DA h_JC h_JNC h_JB h_JNB h_JBC h_JZ h_JNZ h_CJNE h_DJNZ h_ANL h_ORL h_XRL h_CLR h_CPL h_RL h_RLC h_RR h_RRC h_SWAP h_MOV h_MOVX h_SETB h_PUSH h_POP h_XCH h_XCHD h_RET h_RETI h_NOP h_JMP = function
2365 | ADD (x_864, x_863) -> h_ADD x_864 x_863
2366 | ADDC (x_866, x_865) -> h_ADDC x_866 x_865
2367 | SUBB (x_868, x_867) -> h_SUBB x_868 x_867
2368 | INC x_869 -> h_INC x_869
2369 | DEC x_870 -> h_DEC x_870
2370 | MUL (x_872, x_871) -> h_MUL x_872 x_871
2371 | DIV (x_874, x_873) -> h_DIV x_874 x_873
2372 | DA x_875 -> h_DA x_875
2373 | JC x_876 -> h_JC x_876
2374 | JNC x_877 -> h_JNC x_877
2375 | JB (x_879, x_878) -> h_JB x_879 x_878
2376 | JNB (x_881, x_880) -> h_JNB x_881 x_880
2377 | JBC (x_883, x_882) -> h_JBC x_883 x_882
2378 | JZ x_884 -> h_JZ x_884
2379 | JNZ x_885 -> h_JNZ x_885
2380 | CJNE (x_887, x_886) -> h_CJNE x_887 x_886
2381 | DJNZ (x_889, x_888) -> h_DJNZ x_889 x_888
2382 | ANL x_890 -> h_ANL x_890
2383 | ORL x_891 -> h_ORL x_891
2384 | XRL x_892 -> h_XRL x_892
2385 | CLR x_893 -> h_CLR x_893
2386 | CPL x_894 -> h_CPL x_894
2387 | RL x_895 -> h_RL x_895
2388 | RLC x_896 -> h_RLC x_896
2389 | RR x_897 -> h_RR x_897
2390 | RRC x_898 -> h_RRC x_898
2391 | SWAP x_899 -> h_SWAP x_899
2392 | MOV x_900 -> h_MOV x_900
2393 | MOVX x_901 -> h_MOVX x_901
2394 | SETB x_902 -> h_SETB x_902
2395 | PUSH x_903 -> h_PUSH x_903
2396 | POP x_904 -> h_POP x_904
2397 | XCH (x_906, x_905) -> h_XCH x_906 x_905
2398 | XCHD (x_908, x_907) -> h_XCHD x_908 x_907
2402 | JMP x_909 -> h_JMP x_909
2404 (** val preinstruction_rect_Type3 :
2405 (subaddressing_mode -> subaddressing_mode -> 'a2) -> (subaddressing_mode
2406 -> subaddressing_mode -> 'a2) -> (subaddressing_mode ->
2407 subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2408 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> subaddressing_mode
2409 -> 'a2) -> (subaddressing_mode -> subaddressing_mode -> 'a2) ->
2410 (subaddressing_mode -> 'a2) -> ('a1 -> 'a2) -> ('a1 -> 'a2) ->
2411 (subaddressing_mode -> 'a1 -> 'a2) -> (subaddressing_mode -> 'a1 -> 'a2)
2412 -> (subaddressing_mode -> 'a1 -> 'a2) -> ('a1 -> 'a2) -> ('a1 -> 'a2) ->
2413 (((subaddressing_mode, subaddressing_mode) Types.prod,
2414 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> 'a1 ->
2415 'a2) -> (subaddressing_mode -> 'a1 -> 'a2) -> ((((subaddressing_mode,
2416 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2417 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2418 Types.prod) Types.sum -> 'a2) -> ((((subaddressing_mode,
2419 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2420 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2421 Types.prod) Types.sum -> 'a2) -> (((subaddressing_mode,
2422 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2423 Types.prod) Types.sum -> 'a2) -> (subaddressing_mode -> 'a2) ->
2424 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2425 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2426 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2427 (((((((subaddressing_mode, subaddressing_mode) Types.prod,
2428 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2429 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2430 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2431 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2432 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> 'a2) ->
2433 (((subaddressing_mode, subaddressing_mode) Types.prod,
2434 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> 'a2) ->
2435 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2436 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> subaddressing_mode
2437 -> 'a2) -> (subaddressing_mode -> subaddressing_mode -> 'a2) -> 'a2 ->
2438 'a2 -> 'a2 -> (subaddressing_mode -> 'a2) -> 'a1 preinstruction -> 'a2 **)
2439 let rec preinstruction_rect_Type3 h_ADD h_ADDC h_SUBB h_INC h_DEC h_MUL h_DIV h_DA h_JC h_JNC h_JB h_JNB h_JBC h_JZ h_JNZ h_CJNE h_DJNZ h_ANL h_ORL h_XRL h_CLR h_CPL h_RL h_RLC h_RR h_RRC h_SWAP h_MOV h_MOVX h_SETB h_PUSH h_POP h_XCH h_XCHD h_RET h_RETI h_NOP h_JMP = function
2440 | ADD (x_950, x_949) -> h_ADD x_950 x_949
2441 | ADDC (x_952, x_951) -> h_ADDC x_952 x_951
2442 | SUBB (x_954, x_953) -> h_SUBB x_954 x_953
2443 | INC x_955 -> h_INC x_955
2444 | DEC x_956 -> h_DEC x_956
2445 | MUL (x_958, x_957) -> h_MUL x_958 x_957
2446 | DIV (x_960, x_959) -> h_DIV x_960 x_959
2447 | DA x_961 -> h_DA x_961
2448 | JC x_962 -> h_JC x_962
2449 | JNC x_963 -> h_JNC x_963
2450 | JB (x_965, x_964) -> h_JB x_965 x_964
2451 | JNB (x_967, x_966) -> h_JNB x_967 x_966
2452 | JBC (x_969, x_968) -> h_JBC x_969 x_968
2453 | JZ x_970 -> h_JZ x_970
2454 | JNZ x_971 -> h_JNZ x_971
2455 | CJNE (x_973, x_972) -> h_CJNE x_973 x_972
2456 | DJNZ (x_975, x_974) -> h_DJNZ x_975 x_974
2457 | ANL x_976 -> h_ANL x_976
2458 | ORL x_977 -> h_ORL x_977
2459 | XRL x_978 -> h_XRL x_978
2460 | CLR x_979 -> h_CLR x_979
2461 | CPL x_980 -> h_CPL x_980
2462 | RL x_981 -> h_RL x_981
2463 | RLC x_982 -> h_RLC x_982
2464 | RR x_983 -> h_RR x_983
2465 | RRC x_984 -> h_RRC x_984
2466 | SWAP x_985 -> h_SWAP x_985
2467 | MOV x_986 -> h_MOV x_986
2468 | MOVX x_987 -> h_MOVX x_987
2469 | SETB x_988 -> h_SETB x_988
2470 | PUSH x_989 -> h_PUSH x_989
2471 | POP x_990 -> h_POP x_990
2472 | XCH (x_992, x_991) -> h_XCH x_992 x_991
2473 | XCHD (x_994, x_993) -> h_XCHD x_994 x_993
2477 | JMP x_995 -> h_JMP x_995
2479 (** val preinstruction_rect_Type2 :
2480 (subaddressing_mode -> subaddressing_mode -> 'a2) -> (subaddressing_mode
2481 -> subaddressing_mode -> 'a2) -> (subaddressing_mode ->
2482 subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2483 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> subaddressing_mode
2484 -> 'a2) -> (subaddressing_mode -> subaddressing_mode -> 'a2) ->
2485 (subaddressing_mode -> 'a2) -> ('a1 -> 'a2) -> ('a1 -> 'a2) ->
2486 (subaddressing_mode -> 'a1 -> 'a2) -> (subaddressing_mode -> 'a1 -> 'a2)
2487 -> (subaddressing_mode -> 'a1 -> 'a2) -> ('a1 -> 'a2) -> ('a1 -> 'a2) ->
2488 (((subaddressing_mode, subaddressing_mode) Types.prod,
2489 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> 'a1 ->
2490 'a2) -> (subaddressing_mode -> 'a1 -> 'a2) -> ((((subaddressing_mode,
2491 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2492 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2493 Types.prod) Types.sum -> 'a2) -> ((((subaddressing_mode,
2494 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2495 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2496 Types.prod) Types.sum -> 'a2) -> (((subaddressing_mode,
2497 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2498 Types.prod) Types.sum -> 'a2) -> (subaddressing_mode -> 'a2) ->
2499 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2500 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2501 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2502 (((((((subaddressing_mode, subaddressing_mode) Types.prod,
2503 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2504 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2505 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2506 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2507 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> 'a2) ->
2508 (((subaddressing_mode, subaddressing_mode) Types.prod,
2509 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> 'a2) ->
2510 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2511 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> subaddressing_mode
2512 -> 'a2) -> (subaddressing_mode -> subaddressing_mode -> 'a2) -> 'a2 ->
2513 'a2 -> 'a2 -> (subaddressing_mode -> 'a2) -> 'a1 preinstruction -> 'a2 **)
2514 let rec preinstruction_rect_Type2 h_ADD h_ADDC h_SUBB h_INC h_DEC h_MUL h_DIV h_DA h_JC h_JNC h_JB h_JNB h_JBC h_JZ h_JNZ h_CJNE h_DJNZ h_ANL h_ORL h_XRL h_CLR h_CPL h_RL h_RLC h_RR h_RRC h_SWAP h_MOV h_MOVX h_SETB h_PUSH h_POP h_XCH h_XCHD h_RET h_RETI h_NOP h_JMP = function
2515 | ADD (x_1036, x_1035) -> h_ADD x_1036 x_1035
2516 | ADDC (x_1038, x_1037) -> h_ADDC x_1038 x_1037
2517 | SUBB (x_1040, x_1039) -> h_SUBB x_1040 x_1039
2518 | INC x_1041 -> h_INC x_1041
2519 | DEC x_1042 -> h_DEC x_1042
2520 | MUL (x_1044, x_1043) -> h_MUL x_1044 x_1043
2521 | DIV (x_1046, x_1045) -> h_DIV x_1046 x_1045
2522 | DA x_1047 -> h_DA x_1047
2523 | JC x_1048 -> h_JC x_1048
2524 | JNC x_1049 -> h_JNC x_1049
2525 | JB (x_1051, x_1050) -> h_JB x_1051 x_1050
2526 | JNB (x_1053, x_1052) -> h_JNB x_1053 x_1052
2527 | JBC (x_1055, x_1054) -> h_JBC x_1055 x_1054
2528 | JZ x_1056 -> h_JZ x_1056
2529 | JNZ x_1057 -> h_JNZ x_1057
2530 | CJNE (x_1059, x_1058) -> h_CJNE x_1059 x_1058
2531 | DJNZ (x_1061, x_1060) -> h_DJNZ x_1061 x_1060
2532 | ANL x_1062 -> h_ANL x_1062
2533 | ORL x_1063 -> h_ORL x_1063
2534 | XRL x_1064 -> h_XRL x_1064
2535 | CLR x_1065 -> h_CLR x_1065
2536 | CPL x_1066 -> h_CPL x_1066
2537 | RL x_1067 -> h_RL x_1067
2538 | RLC x_1068 -> h_RLC x_1068
2539 | RR x_1069 -> h_RR x_1069
2540 | RRC x_1070 -> h_RRC x_1070
2541 | SWAP x_1071 -> h_SWAP x_1071
2542 | MOV x_1072 -> h_MOV x_1072
2543 | MOVX x_1073 -> h_MOVX x_1073
2544 | SETB x_1074 -> h_SETB x_1074
2545 | PUSH x_1075 -> h_PUSH x_1075
2546 | POP x_1076 -> h_POP x_1076
2547 | XCH (x_1078, x_1077) -> h_XCH x_1078 x_1077
2548 | XCHD (x_1080, x_1079) -> h_XCHD x_1080 x_1079
2552 | JMP x_1081 -> h_JMP x_1081
2554 (** val preinstruction_rect_Type1 :
2555 (subaddressing_mode -> subaddressing_mode -> 'a2) -> (subaddressing_mode
2556 -> subaddressing_mode -> 'a2) -> (subaddressing_mode ->
2557 subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2558 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> subaddressing_mode
2559 -> 'a2) -> (subaddressing_mode -> subaddressing_mode -> 'a2) ->
2560 (subaddressing_mode -> 'a2) -> ('a1 -> 'a2) -> ('a1 -> 'a2) ->
2561 (subaddressing_mode -> 'a1 -> 'a2) -> (subaddressing_mode -> 'a1 -> 'a2)
2562 -> (subaddressing_mode -> 'a1 -> 'a2) -> ('a1 -> 'a2) -> ('a1 -> 'a2) ->
2563 (((subaddressing_mode, subaddressing_mode) Types.prod,
2564 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> 'a1 ->
2565 'a2) -> (subaddressing_mode -> 'a1 -> 'a2) -> ((((subaddressing_mode,
2566 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2567 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2568 Types.prod) Types.sum -> 'a2) -> ((((subaddressing_mode,
2569 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2570 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2571 Types.prod) Types.sum -> 'a2) -> (((subaddressing_mode,
2572 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2573 Types.prod) Types.sum -> 'a2) -> (subaddressing_mode -> 'a2) ->
2574 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2575 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2576 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2577 (((((((subaddressing_mode, subaddressing_mode) Types.prod,
2578 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2579 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2580 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2581 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2582 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> 'a2) ->
2583 (((subaddressing_mode, subaddressing_mode) Types.prod,
2584 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> 'a2) ->
2585 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2586 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> subaddressing_mode
2587 -> 'a2) -> (subaddressing_mode -> subaddressing_mode -> 'a2) -> 'a2 ->
2588 'a2 -> 'a2 -> (subaddressing_mode -> 'a2) -> 'a1 preinstruction -> 'a2 **)
2589 let rec preinstruction_rect_Type1 h_ADD h_ADDC h_SUBB h_INC h_DEC h_MUL h_DIV h_DA h_JC h_JNC h_JB h_JNB h_JBC h_JZ h_JNZ h_CJNE h_DJNZ h_ANL h_ORL h_XRL h_CLR h_CPL h_RL h_RLC h_RR h_RRC h_SWAP h_MOV h_MOVX h_SETB h_PUSH h_POP h_XCH h_XCHD h_RET h_RETI h_NOP h_JMP = function
2590 | ADD (x_1122, x_1121) -> h_ADD x_1122 x_1121
2591 | ADDC (x_1124, x_1123) -> h_ADDC x_1124 x_1123
2592 | SUBB (x_1126, x_1125) -> h_SUBB x_1126 x_1125
2593 | INC x_1127 -> h_INC x_1127
2594 | DEC x_1128 -> h_DEC x_1128
2595 | MUL (x_1130, x_1129) -> h_MUL x_1130 x_1129
2596 | DIV (x_1132, x_1131) -> h_DIV x_1132 x_1131
2597 | DA x_1133 -> h_DA x_1133
2598 | JC x_1134 -> h_JC x_1134
2599 | JNC x_1135 -> h_JNC x_1135
2600 | JB (x_1137, x_1136) -> h_JB x_1137 x_1136
2601 | JNB (x_1139, x_1138) -> h_JNB x_1139 x_1138
2602 | JBC (x_1141, x_1140) -> h_JBC x_1141 x_1140
2603 | JZ x_1142 -> h_JZ x_1142
2604 | JNZ x_1143 -> h_JNZ x_1143
2605 | CJNE (x_1145, x_1144) -> h_CJNE x_1145 x_1144
2606 | DJNZ (x_1147, x_1146) -> h_DJNZ x_1147 x_1146
2607 | ANL x_1148 -> h_ANL x_1148
2608 | ORL x_1149 -> h_ORL x_1149
2609 | XRL x_1150 -> h_XRL x_1150
2610 | CLR x_1151 -> h_CLR x_1151
2611 | CPL x_1152 -> h_CPL x_1152
2612 | RL x_1153 -> h_RL x_1153
2613 | RLC x_1154 -> h_RLC x_1154
2614 | RR x_1155 -> h_RR x_1155
2615 | RRC x_1156 -> h_RRC x_1156
2616 | SWAP x_1157 -> h_SWAP x_1157
2617 | MOV x_1158 -> h_MOV x_1158
2618 | MOVX x_1159 -> h_MOVX x_1159
2619 | SETB x_1160 -> h_SETB x_1160
2620 | PUSH x_1161 -> h_PUSH x_1161
2621 | POP x_1162 -> h_POP x_1162
2622 | XCH (x_1164, x_1163) -> h_XCH x_1164 x_1163
2623 | XCHD (x_1166, x_1165) -> h_XCHD x_1166 x_1165
2627 | JMP x_1167 -> h_JMP x_1167
2629 (** val preinstruction_rect_Type0 :
2630 (subaddressing_mode -> subaddressing_mode -> 'a2) -> (subaddressing_mode
2631 -> subaddressing_mode -> 'a2) -> (subaddressing_mode ->
2632 subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2633 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> subaddressing_mode
2634 -> 'a2) -> (subaddressing_mode -> subaddressing_mode -> 'a2) ->
2635 (subaddressing_mode -> 'a2) -> ('a1 -> 'a2) -> ('a1 -> 'a2) ->
2636 (subaddressing_mode -> 'a1 -> 'a2) -> (subaddressing_mode -> 'a1 -> 'a2)
2637 -> (subaddressing_mode -> 'a1 -> 'a2) -> ('a1 -> 'a2) -> ('a1 -> 'a2) ->
2638 (((subaddressing_mode, subaddressing_mode) Types.prod,
2639 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> 'a1 ->
2640 'a2) -> (subaddressing_mode -> 'a1 -> 'a2) -> ((((subaddressing_mode,
2641 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2642 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2643 Types.prod) Types.sum -> 'a2) -> ((((subaddressing_mode,
2644 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2645 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2646 Types.prod) Types.sum -> 'a2) -> (((subaddressing_mode,
2647 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2648 Types.prod) Types.sum -> 'a2) -> (subaddressing_mode -> 'a2) ->
2649 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2650 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2651 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2652 (((((((subaddressing_mode, subaddressing_mode) Types.prod,
2653 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2654 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2655 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2656 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2657 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> 'a2) ->
2658 (((subaddressing_mode, subaddressing_mode) Types.prod,
2659 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> 'a2) ->
2660 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> 'a2) ->
2661 (subaddressing_mode -> 'a2) -> (subaddressing_mode -> subaddressing_mode
2662 -> 'a2) -> (subaddressing_mode -> subaddressing_mode -> 'a2) -> 'a2 ->
2663 'a2 -> 'a2 -> (subaddressing_mode -> 'a2) -> 'a1 preinstruction -> 'a2 **)
2664 let rec preinstruction_rect_Type0 h_ADD h_ADDC h_SUBB h_INC h_DEC h_MUL h_DIV h_DA h_JC h_JNC h_JB h_JNB h_JBC h_JZ h_JNZ h_CJNE h_DJNZ h_ANL h_ORL h_XRL h_CLR h_CPL h_RL h_RLC h_RR h_RRC h_SWAP h_MOV h_MOVX h_SETB h_PUSH h_POP h_XCH h_XCHD h_RET h_RETI h_NOP h_JMP = function
2665 | ADD (x_1208, x_1207) -> h_ADD x_1208 x_1207
2666 | ADDC (x_1210, x_1209) -> h_ADDC x_1210 x_1209
2667 | SUBB (x_1212, x_1211) -> h_SUBB x_1212 x_1211
2668 | INC x_1213 -> h_INC x_1213
2669 | DEC x_1214 -> h_DEC x_1214
2670 | MUL (x_1216, x_1215) -> h_MUL x_1216 x_1215
2671 | DIV (x_1218, x_1217) -> h_DIV x_1218 x_1217
2672 | DA x_1219 -> h_DA x_1219
2673 | JC x_1220 -> h_JC x_1220
2674 | JNC x_1221 -> h_JNC x_1221
2675 | JB (x_1223, x_1222) -> h_JB x_1223 x_1222
2676 | JNB (x_1225, x_1224) -> h_JNB x_1225 x_1224
2677 | JBC (x_1227, x_1226) -> h_JBC x_1227 x_1226
2678 | JZ x_1228 -> h_JZ x_1228
2679 | JNZ x_1229 -> h_JNZ x_1229
2680 | CJNE (x_1231, x_1230) -> h_CJNE x_1231 x_1230
2681 | DJNZ (x_1233, x_1232) -> h_DJNZ x_1233 x_1232
2682 | ANL x_1234 -> h_ANL x_1234
2683 | ORL x_1235 -> h_ORL x_1235
2684 | XRL x_1236 -> h_XRL x_1236
2685 | CLR x_1237 -> h_CLR x_1237
2686 | CPL x_1238 -> h_CPL x_1238
2687 | RL x_1239 -> h_RL x_1239
2688 | RLC x_1240 -> h_RLC x_1240
2689 | RR x_1241 -> h_RR x_1241
2690 | RRC x_1242 -> h_RRC x_1242
2691 | SWAP x_1243 -> h_SWAP x_1243
2692 | MOV x_1244 -> h_MOV x_1244
2693 | MOVX x_1245 -> h_MOVX x_1245
2694 | SETB x_1246 -> h_SETB x_1246
2695 | PUSH x_1247 -> h_PUSH x_1247
2696 | POP x_1248 -> h_POP x_1248
2697 | XCH (x_1250, x_1249) -> h_XCH x_1250 x_1249
2698 | XCHD (x_1252, x_1251) -> h_XCHD x_1252 x_1251
2702 | JMP x_1253 -> h_JMP x_1253
2704 (** val preinstruction_inv_rect_Type4 :
2705 'a1 preinstruction -> (subaddressing_mode -> subaddressing_mode -> __ ->
2706 'a2) -> (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2707 (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2708 (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ -> 'a2) ->
2709 (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2710 (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2711 (subaddressing_mode -> __ -> 'a2) -> ('a1 -> __ -> 'a2) -> ('a1 -> __ ->
2712 'a2) -> (subaddressing_mode -> 'a1 -> __ -> 'a2) -> (subaddressing_mode
2713 -> 'a1 -> __ -> 'a2) -> (subaddressing_mode -> 'a1 -> __ -> 'a2) -> ('a1
2714 -> __ -> 'a2) -> ('a1 -> __ -> 'a2) -> (((subaddressing_mode,
2715 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2716 Types.prod) Types.sum -> 'a1 -> __ -> 'a2) -> (subaddressing_mode -> 'a1
2717 -> __ -> 'a2) -> ((((subaddressing_mode, subaddressing_mode) Types.prod,
2718 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2719 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> __ ->
2720 'a2) -> ((((subaddressing_mode, subaddressing_mode) Types.prod,
2721 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2722 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> __ ->
2723 'a2) -> (((subaddressing_mode, subaddressing_mode) Types.prod,
2724 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> __ ->
2725 'a2) -> (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ ->
2726 'a2) -> (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ ->
2727 'a2) -> (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ ->
2728 'a2) -> (subaddressing_mode -> __ -> 'a2) -> (((((((subaddressing_mode,
2729 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2730 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2731 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2732 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2733 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2734 Types.prod) Types.sum -> __ -> 'a2) -> (((subaddressing_mode,
2735 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2736 Types.prod) Types.sum -> __ -> 'a2) -> (subaddressing_mode -> __ -> 'a2)
2737 -> (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ -> 'a2)
2738 -> (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2739 (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) -> (__ -> 'a2) ->
2740 (__ -> 'a2) -> (__ -> 'a2) -> (subaddressing_mode -> __ -> 'a2) -> 'a2 **)
2741 let preinstruction_inv_rect_Type4 hterm h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 h20 h21 h22 h23 h24 h25 h26 h27 h28 h29 h30 h31 h32 h33 h34 h35 h36 h37 h38 =
2743 preinstruction_rect_Type4 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14
2744 h15 h16 h17 h18 h19 h20 h21 h22 h23 h24 h25 h26 h27 h28 h29 h30 h31 h32
2745 h33 h34 h35 h36 h37 h38 hterm
2749 (** val preinstruction_inv_rect_Type3 :
2750 'a1 preinstruction -> (subaddressing_mode -> subaddressing_mode -> __ ->
2751 'a2) -> (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2752 (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2753 (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ -> 'a2) ->
2754 (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2755 (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2756 (subaddressing_mode -> __ -> 'a2) -> ('a1 -> __ -> 'a2) -> ('a1 -> __ ->
2757 'a2) -> (subaddressing_mode -> 'a1 -> __ -> 'a2) -> (subaddressing_mode
2758 -> 'a1 -> __ -> 'a2) -> (subaddressing_mode -> 'a1 -> __ -> 'a2) -> ('a1
2759 -> __ -> 'a2) -> ('a1 -> __ -> 'a2) -> (((subaddressing_mode,
2760 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2761 Types.prod) Types.sum -> 'a1 -> __ -> 'a2) -> (subaddressing_mode -> 'a1
2762 -> __ -> 'a2) -> ((((subaddressing_mode, subaddressing_mode) Types.prod,
2763 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2764 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> __ ->
2765 'a2) -> ((((subaddressing_mode, subaddressing_mode) Types.prod,
2766 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2767 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> __ ->
2768 'a2) -> (((subaddressing_mode, subaddressing_mode) Types.prod,
2769 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> __ ->
2770 'a2) -> (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ ->
2771 'a2) -> (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ ->
2772 'a2) -> (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ ->
2773 'a2) -> (subaddressing_mode -> __ -> 'a2) -> (((((((subaddressing_mode,
2774 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2775 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2776 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2777 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2778 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2779 Types.prod) Types.sum -> __ -> 'a2) -> (((subaddressing_mode,
2780 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2781 Types.prod) Types.sum -> __ -> 'a2) -> (subaddressing_mode -> __ -> 'a2)
2782 -> (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ -> 'a2)
2783 -> (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2784 (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) -> (__ -> 'a2) ->
2785 (__ -> 'a2) -> (__ -> 'a2) -> (subaddressing_mode -> __ -> 'a2) -> 'a2 **)
2786 let preinstruction_inv_rect_Type3 hterm h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 h20 h21 h22 h23 h24 h25 h26 h27 h28 h29 h30 h31 h32 h33 h34 h35 h36 h37 h38 =
2788 preinstruction_rect_Type3 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14
2789 h15 h16 h17 h18 h19 h20 h21 h22 h23 h24 h25 h26 h27 h28 h29 h30 h31 h32
2790 h33 h34 h35 h36 h37 h38 hterm
2794 (** val preinstruction_inv_rect_Type2 :
2795 'a1 preinstruction -> (subaddressing_mode -> subaddressing_mode -> __ ->
2796 'a2) -> (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2797 (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2798 (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ -> 'a2) ->
2799 (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2800 (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2801 (subaddressing_mode -> __ -> 'a2) -> ('a1 -> __ -> 'a2) -> ('a1 -> __ ->
2802 'a2) -> (subaddressing_mode -> 'a1 -> __ -> 'a2) -> (subaddressing_mode
2803 -> 'a1 -> __ -> 'a2) -> (subaddressing_mode -> 'a1 -> __ -> 'a2) -> ('a1
2804 -> __ -> 'a2) -> ('a1 -> __ -> 'a2) -> (((subaddressing_mode,
2805 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2806 Types.prod) Types.sum -> 'a1 -> __ -> 'a2) -> (subaddressing_mode -> 'a1
2807 -> __ -> 'a2) -> ((((subaddressing_mode, subaddressing_mode) Types.prod,
2808 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2809 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> __ ->
2810 'a2) -> ((((subaddressing_mode, subaddressing_mode) Types.prod,
2811 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2812 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> __ ->
2813 'a2) -> (((subaddressing_mode, subaddressing_mode) Types.prod,
2814 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> __ ->
2815 'a2) -> (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ ->
2816 'a2) -> (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ ->
2817 'a2) -> (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ ->
2818 'a2) -> (subaddressing_mode -> __ -> 'a2) -> (((((((subaddressing_mode,
2819 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2820 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2821 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2822 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2823 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2824 Types.prod) Types.sum -> __ -> 'a2) -> (((subaddressing_mode,
2825 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2826 Types.prod) Types.sum -> __ -> 'a2) -> (subaddressing_mode -> __ -> 'a2)
2827 -> (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ -> 'a2)
2828 -> (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2829 (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) -> (__ -> 'a2) ->
2830 (__ -> 'a2) -> (__ -> 'a2) -> (subaddressing_mode -> __ -> 'a2) -> 'a2 **)
2831 let preinstruction_inv_rect_Type2 hterm h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 h20 h21 h22 h23 h24 h25 h26 h27 h28 h29 h30 h31 h32 h33 h34 h35 h36 h37 h38 =
2833 preinstruction_rect_Type2 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14
2834 h15 h16 h17 h18 h19 h20 h21 h22 h23 h24 h25 h26 h27 h28 h29 h30 h31 h32
2835 h33 h34 h35 h36 h37 h38 hterm
2839 (** val preinstruction_inv_rect_Type1 :
2840 'a1 preinstruction -> (subaddressing_mode -> subaddressing_mode -> __ ->
2841 'a2) -> (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2842 (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2843 (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ -> 'a2) ->
2844 (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2845 (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2846 (subaddressing_mode -> __ -> 'a2) -> ('a1 -> __ -> 'a2) -> ('a1 -> __ ->
2847 'a2) -> (subaddressing_mode -> 'a1 -> __ -> 'a2) -> (subaddressing_mode
2848 -> 'a1 -> __ -> 'a2) -> (subaddressing_mode -> 'a1 -> __ -> 'a2) -> ('a1
2849 -> __ -> 'a2) -> ('a1 -> __ -> 'a2) -> (((subaddressing_mode,
2850 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2851 Types.prod) Types.sum -> 'a1 -> __ -> 'a2) -> (subaddressing_mode -> 'a1
2852 -> __ -> 'a2) -> ((((subaddressing_mode, subaddressing_mode) Types.prod,
2853 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2854 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> __ ->
2855 'a2) -> ((((subaddressing_mode, subaddressing_mode) Types.prod,
2856 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2857 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> __ ->
2858 'a2) -> (((subaddressing_mode, subaddressing_mode) Types.prod,
2859 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> __ ->
2860 'a2) -> (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ ->
2861 'a2) -> (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ ->
2862 'a2) -> (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ ->
2863 'a2) -> (subaddressing_mode -> __ -> 'a2) -> (((((((subaddressing_mode,
2864 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2865 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2866 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2867 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2868 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2869 Types.prod) Types.sum -> __ -> 'a2) -> (((subaddressing_mode,
2870 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2871 Types.prod) Types.sum -> __ -> 'a2) -> (subaddressing_mode -> __ -> 'a2)
2872 -> (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ -> 'a2)
2873 -> (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2874 (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) -> (__ -> 'a2) ->
2875 (__ -> 'a2) -> (__ -> 'a2) -> (subaddressing_mode -> __ -> 'a2) -> 'a2 **)
2876 let preinstruction_inv_rect_Type1 hterm h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 h20 h21 h22 h23 h24 h25 h26 h27 h28 h29 h30 h31 h32 h33 h34 h35 h36 h37 h38 =
2878 preinstruction_rect_Type1 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14
2879 h15 h16 h17 h18 h19 h20 h21 h22 h23 h24 h25 h26 h27 h28 h29 h30 h31 h32
2880 h33 h34 h35 h36 h37 h38 hterm
2884 (** val preinstruction_inv_rect_Type0 :
2885 'a1 preinstruction -> (subaddressing_mode -> subaddressing_mode -> __ ->
2886 'a2) -> (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2887 (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2888 (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ -> 'a2) ->
2889 (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2890 (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2891 (subaddressing_mode -> __ -> 'a2) -> ('a1 -> __ -> 'a2) -> ('a1 -> __ ->
2892 'a2) -> (subaddressing_mode -> 'a1 -> __ -> 'a2) -> (subaddressing_mode
2893 -> 'a1 -> __ -> 'a2) -> (subaddressing_mode -> 'a1 -> __ -> 'a2) -> ('a1
2894 -> __ -> 'a2) -> ('a1 -> __ -> 'a2) -> (((subaddressing_mode,
2895 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2896 Types.prod) Types.sum -> 'a1 -> __ -> 'a2) -> (subaddressing_mode -> 'a1
2897 -> __ -> 'a2) -> ((((subaddressing_mode, subaddressing_mode) Types.prod,
2898 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2899 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> __ ->
2900 'a2) -> ((((subaddressing_mode, subaddressing_mode) Types.prod,
2901 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum,
2902 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> __ ->
2903 'a2) -> (((subaddressing_mode, subaddressing_mode) Types.prod,
2904 (subaddressing_mode, subaddressing_mode) Types.prod) Types.sum -> __ ->
2905 'a2) -> (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ ->
2906 'a2) -> (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ ->
2907 'a2) -> (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ ->
2908 'a2) -> (subaddressing_mode -> __ -> 'a2) -> (((((((subaddressing_mode,
2909 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2910 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2911 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2912 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2913 Types.prod) Types.sum, (subaddressing_mode, subaddressing_mode)
2914 Types.prod) Types.sum -> __ -> 'a2) -> (((subaddressing_mode,
2915 subaddressing_mode) Types.prod, (subaddressing_mode, subaddressing_mode)
2916 Types.prod) Types.sum -> __ -> 'a2) -> (subaddressing_mode -> __ -> 'a2)
2917 -> (subaddressing_mode -> __ -> 'a2) -> (subaddressing_mode -> __ -> 'a2)
2918 -> (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) ->
2919 (subaddressing_mode -> subaddressing_mode -> __ -> 'a2) -> (__ -> 'a2) ->
2920 (__ -> 'a2) -> (__ -> 'a2) -> (subaddressing_mode -> __ -> 'a2) -> 'a2 **)
2921 let preinstruction_inv_rect_Type0 hterm h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 h20 h21 h22 h23 h24 h25 h26 h27 h28 h29 h30 h31 h32 h33 h34 h35 h36 h37 h38 =
2923 preinstruction_rect_Type0 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14
2924 h15 h16 h17 h18 h19 h20 h21 h22 h23 h24 h25 h26 h27 h28 h29 h30 h31 h32
2925 h33 h34 h35 h36 h37 h38 hterm
2929 (** val preinstruction_discr :
2930 'a1 preinstruction -> 'a1 preinstruction -> __ **)
2931 let preinstruction_discr x y =
2932 Logic.eq_rect_Type2 x
2934 | ADD (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2935 | ADDC (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2936 | SUBB (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2937 | INC a0 -> Obj.magic (fun _ dH -> dH __)
2938 | DEC a0 -> Obj.magic (fun _ dH -> dH __)
2939 | MUL (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2940 | DIV (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2941 | DA a0 -> Obj.magic (fun _ dH -> dH __)
2942 | JC a0 -> Obj.magic (fun _ dH -> dH __)
2943 | JNC a0 -> Obj.magic (fun _ dH -> dH __)
2944 | JB (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2945 | JNB (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2946 | JBC (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2947 | JZ a0 -> Obj.magic (fun _ dH -> dH __)
2948 | JNZ a0 -> Obj.magic (fun _ dH -> dH __)
2949 | CJNE (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2950 | DJNZ (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2951 | ANL a0 -> Obj.magic (fun _ dH -> dH __)
2952 | ORL a0 -> Obj.magic (fun _ dH -> dH __)
2953 | XRL a0 -> Obj.magic (fun _ dH -> dH __)
2954 | CLR a0 -> Obj.magic (fun _ dH -> dH __)
2955 | CPL a0 -> Obj.magic (fun _ dH -> dH __)
2956 | RL a0 -> Obj.magic (fun _ dH -> dH __)
2957 | RLC a0 -> Obj.magic (fun _ dH -> dH __)
2958 | RR a0 -> Obj.magic (fun _ dH -> dH __)
2959 | RRC a0 -> Obj.magic (fun _ dH -> dH __)
2960 | SWAP a0 -> Obj.magic (fun _ dH -> dH __)
2961 | MOV a0 -> Obj.magic (fun _ dH -> dH __)
2962 | MOVX a0 -> Obj.magic (fun _ dH -> dH __)
2963 | SETB a0 -> Obj.magic (fun _ dH -> dH __)
2964 | PUSH a0 -> Obj.magic (fun _ dH -> dH __)
2965 | POP a0 -> Obj.magic (fun _ dH -> dH __)
2966 | XCH (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2967 | XCHD (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2968 | RET -> Obj.magic (fun _ dH -> dH)
2969 | RETI -> Obj.magic (fun _ dH -> dH)
2970 | NOP -> Obj.magic (fun _ dH -> dH)
2971 | JMP a0 -> Obj.magic (fun _ dH -> dH __)) y
2973 (** val preinstruction_jmdiscr :
2974 'a1 preinstruction -> 'a1 preinstruction -> __ **)
2975 let preinstruction_jmdiscr x y =
2976 Logic.eq_rect_Type2 x
2978 | ADD (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2979 | ADDC (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2980 | SUBB (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2981 | INC a0 -> Obj.magic (fun _ dH -> dH __)
2982 | DEC a0 -> Obj.magic (fun _ dH -> dH __)
2983 | MUL (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2984 | DIV (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2985 | DA a0 -> Obj.magic (fun _ dH -> dH __)
2986 | JC a0 -> Obj.magic (fun _ dH -> dH __)
2987 | JNC a0 -> Obj.magic (fun _ dH -> dH __)
2988 | JB (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2989 | JNB (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2990 | JBC (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2991 | JZ a0 -> Obj.magic (fun _ dH -> dH __)
2992 | JNZ a0 -> Obj.magic (fun _ dH -> dH __)
2993 | CJNE (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2994 | DJNZ (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
2995 | ANL a0 -> Obj.magic (fun _ dH -> dH __)
2996 | ORL a0 -> Obj.magic (fun _ dH -> dH __)
2997 | XRL a0 -> Obj.magic (fun _ dH -> dH __)
2998 | CLR a0 -> Obj.magic (fun _ dH -> dH __)
2999 | CPL a0 -> Obj.magic (fun _ dH -> dH __)
3000 | RL a0 -> Obj.magic (fun _ dH -> dH __)
3001 | RLC a0 -> Obj.magic (fun _ dH -> dH __)
3002 | RR a0 -> Obj.magic (fun _ dH -> dH __)
3003 | RRC a0 -> Obj.magic (fun _ dH -> dH __)
3004 | SWAP a0 -> Obj.magic (fun _ dH -> dH __)
3005 | MOV a0 -> Obj.magic (fun _ dH -> dH __)
3006 | MOVX a0 -> Obj.magic (fun _ dH -> dH __)
3007 | SETB a0 -> Obj.magic (fun _ dH -> dH __)
3008 | PUSH a0 -> Obj.magic (fun _ dH -> dH __)
3009 | POP a0 -> Obj.magic (fun _ dH -> dH __)
3010 | XCH (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
3011 | XCHD (a0, a10) -> Obj.magic (fun _ dH -> dH __ __)
3012 | RET -> Obj.magic (fun _ dH -> dH)
3013 | RETI -> Obj.magic (fun _ dH -> dH)
3014 | NOP -> Obj.magic (fun _ dH -> dH)
3015 | JMP a0 -> Obj.magic (fun _ dH -> dH __)) y
3017 (** val eq_preinstruction :
3018 subaddressing_mode preinstruction -> subaddressing_mode preinstruction ->
3020 let eq_preinstruction i j =
3022 | ADD (arg1, arg2) ->
3024 | ADD (arg1', arg2') ->
3027 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
3028 Vector.VEmpty)) arg1)
3029 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
3030 Vector.VEmpty)) arg1'))
3032 (subaddressing_modeel (Nat.S (Nat.S (Nat.S Nat.O))) (Vector.VCons
3033 ((Nat.S (Nat.S (Nat.S Nat.O))), Registr, (Vector.VCons ((Nat.S
3034 (Nat.S Nat.O)), Direct, (Vector.VCons ((Nat.S Nat.O), Indirect,
3035 (Vector.VCons (Nat.O, Data, Vector.VEmpty)))))))) arg2)
3036 (subaddressing_modeel (Nat.S (Nat.S (Nat.S Nat.O))) (Vector.VCons
3037 ((Nat.S (Nat.S (Nat.S Nat.O))), Registr, (Vector.VCons ((Nat.S
3038 (Nat.S Nat.O)), Direct, (Vector.VCons ((Nat.S Nat.O), Indirect,
3039 (Vector.VCons (Nat.O, Data, Vector.VEmpty)))))))) arg2'))
3040 | ADDC (x, x0) -> Bool.False
3041 | SUBB (x, x0) -> Bool.False
3042 | INC x -> Bool.False
3043 | DEC x -> Bool.False
3044 | MUL (x, x0) -> Bool.False
3045 | DIV (x, x0) -> Bool.False
3046 | DA x -> Bool.False
3047 | JC x -> Bool.False
3048 | JNC x -> Bool.False
3049 | JB (x, x0) -> Bool.False
3050 | JNB (x, x0) -> Bool.False
3051 | JBC (x, x0) -> Bool.False
3052 | JZ x -> Bool.False
3053 | JNZ x -> Bool.False
3054 | CJNE (x, x0) -> Bool.False
3055 | DJNZ (x, x0) -> Bool.False
3056 | ANL x -> Bool.False
3057 | ORL x -> Bool.False
3058 | XRL x -> Bool.False
3059 | CLR x -> Bool.False
3060 | CPL x -> Bool.False
3061 | RL x -> Bool.False
3062 | RLC x -> Bool.False
3063 | RR x -> Bool.False
3064 | RRC x -> Bool.False
3065 | SWAP x -> Bool.False
3066 | MOV x -> Bool.False
3067 | MOVX x -> Bool.False
3068 | SETB x -> Bool.False
3069 | PUSH x -> Bool.False
3070 | POP x -> Bool.False
3071 | XCH (x, x0) -> Bool.False
3072 | XCHD (x, x0) -> Bool.False
3074 | RETI -> Bool.False
3076 | JMP x -> Bool.False)
3077 | ADDC (arg1, arg2) ->
3079 | ADD (x, x0) -> Bool.False
3080 | ADDC (arg1', arg2') ->
3083 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
3084 Vector.VEmpty)) arg1)
3085 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
3086 Vector.VEmpty)) arg1'))
3088 (subaddressing_modeel (Nat.S (Nat.S (Nat.S Nat.O))) (Vector.VCons
3089 ((Nat.S (Nat.S (Nat.S Nat.O))), Registr, (Vector.VCons ((Nat.S
3090 (Nat.S Nat.O)), Direct, (Vector.VCons ((Nat.S Nat.O), Indirect,
3091 (Vector.VCons (Nat.O, Data, Vector.VEmpty)))))))) arg2)
3092 (subaddressing_modeel (Nat.S (Nat.S (Nat.S Nat.O))) (Vector.VCons
3093 ((Nat.S (Nat.S (Nat.S Nat.O))), Registr, (Vector.VCons ((Nat.S
3094 (Nat.S Nat.O)), Direct, (Vector.VCons ((Nat.S Nat.O), Indirect,
3095 (Vector.VCons (Nat.O, Data, Vector.VEmpty)))))))) arg2'))
3096 | SUBB (x, x0) -> Bool.False
3097 | INC x -> Bool.False
3098 | DEC x -> Bool.False
3099 | MUL (x, x0) -> Bool.False
3100 | DIV (x, x0) -> Bool.False
3101 | DA x -> Bool.False
3102 | JC x -> Bool.False
3103 | JNC x -> Bool.False
3104 | JB (x, x0) -> Bool.False
3105 | JNB (x, x0) -> Bool.False
3106 | JBC (x, x0) -> Bool.False
3107 | JZ x -> Bool.False
3108 | JNZ x -> Bool.False
3109 | CJNE (x, x0) -> Bool.False
3110 | DJNZ (x, x0) -> Bool.False
3111 | ANL x -> Bool.False
3112 | ORL x -> Bool.False
3113 | XRL x -> Bool.False
3114 | CLR x -> Bool.False
3115 | CPL x -> Bool.False
3116 | RL x -> Bool.False
3117 | RLC x -> Bool.False
3118 | RR x -> Bool.False
3119 | RRC x -> Bool.False
3120 | SWAP x -> Bool.False
3121 | MOV x -> Bool.False
3122 | MOVX x -> Bool.False
3123 | SETB x -> Bool.False
3124 | PUSH x -> Bool.False
3125 | POP x -> Bool.False
3126 | XCH (x, x0) -> Bool.False
3127 | XCHD (x, x0) -> Bool.False
3129 | RETI -> Bool.False
3131 | JMP x -> Bool.False)
3132 | SUBB (arg1, arg2) ->
3134 | ADD (x, x0) -> Bool.False
3135 | ADDC (x, x0) -> Bool.False
3136 | SUBB (arg1', arg2') ->
3139 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
3140 Vector.VEmpty)) arg1)
3141 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
3142 Vector.VEmpty)) arg1'))
3144 (subaddressing_modeel (Nat.S (Nat.S (Nat.S Nat.O))) (Vector.VCons
3145 ((Nat.S (Nat.S (Nat.S Nat.O))), Registr, (Vector.VCons ((Nat.S
3146 (Nat.S Nat.O)), Direct, (Vector.VCons ((Nat.S Nat.O), Indirect,
3147 (Vector.VCons (Nat.O, Data, Vector.VEmpty)))))))) arg2)
3148 (subaddressing_modeel (Nat.S (Nat.S (Nat.S Nat.O))) (Vector.VCons
3149 ((Nat.S (Nat.S (Nat.S Nat.O))), Registr, (Vector.VCons ((Nat.S
3150 (Nat.S Nat.O)), Direct, (Vector.VCons ((Nat.S Nat.O), Indirect,
3151 (Vector.VCons (Nat.O, Data, Vector.VEmpty)))))))) arg2'))
3152 | INC x -> Bool.False
3153 | DEC x -> Bool.False
3154 | MUL (x, x0) -> Bool.False
3155 | DIV (x, x0) -> Bool.False
3156 | DA x -> Bool.False
3157 | JC x -> Bool.False
3158 | JNC x -> Bool.False
3159 | JB (x, x0) -> Bool.False
3160 | JNB (x, x0) -> Bool.False
3161 | JBC (x, x0) -> Bool.False
3162 | JZ x -> Bool.False
3163 | JNZ x -> Bool.False
3164 | CJNE (x, x0) -> Bool.False
3165 | DJNZ (x, x0) -> Bool.False
3166 | ANL x -> Bool.False
3167 | ORL x -> Bool.False
3168 | XRL x -> Bool.False
3169 | CLR x -> Bool.False
3170 | CPL x -> Bool.False
3171 | RL x -> Bool.False
3172 | RLC x -> Bool.False
3173 | RR x -> Bool.False
3174 | RRC x -> Bool.False
3175 | SWAP x -> Bool.False
3176 | MOV x -> Bool.False
3177 | MOVX x -> Bool.False
3178 | SETB x -> Bool.False
3179 | PUSH x -> Bool.False
3180 | POP x -> Bool.False
3181 | XCH (x, x0) -> Bool.False
3182 | XCHD (x, x0) -> Bool.False
3184 | RETI -> Bool.False
3186 | JMP x -> Bool.False)
3189 | ADD (x, x0) -> Bool.False
3190 | ADDC (x, x0) -> Bool.False
3191 | SUBB (x, x0) -> Bool.False
3194 (subaddressing_modeel (Nat.S (Nat.S (Nat.S (Nat.S Nat.O))))
3195 (Vector.VCons ((Nat.S (Nat.S (Nat.S (Nat.S Nat.O)))), Acc_a,
3196 (Vector.VCons ((Nat.S (Nat.S (Nat.S Nat.O))), Registr,
3197 (Vector.VCons ((Nat.S (Nat.S Nat.O)), Direct, (Vector.VCons
3198 ((Nat.S Nat.O), Indirect, (Vector.VCons (Nat.O, Dptr,
3199 Vector.VEmpty)))))))))) arg)
3200 (subaddressing_modeel (Nat.S (Nat.S (Nat.S (Nat.S Nat.O))))
3201 (Vector.VCons ((Nat.S (Nat.S (Nat.S (Nat.S Nat.O)))), Acc_a,
3202 (Vector.VCons ((Nat.S (Nat.S (Nat.S Nat.O))), Registr,
3203 (Vector.VCons ((Nat.S (Nat.S Nat.O)), Direct, (Vector.VCons
3204 ((Nat.S Nat.O), Indirect, (Vector.VCons (Nat.O, Dptr,
3205 Vector.VEmpty)))))))))) arg')
3206 | DEC x -> Bool.False
3207 | MUL (x, x0) -> Bool.False
3208 | DIV (x, x0) -> Bool.False
3209 | DA x -> Bool.False
3210 | JC x -> Bool.False
3211 | JNC x -> Bool.False
3212 | JB (x, x0) -> Bool.False
3213 | JNB (x, x0) -> Bool.False
3214 | JBC (x, x0) -> Bool.False
3215 | JZ x -> Bool.False
3216 | JNZ x -> Bool.False
3217 | CJNE (x, x0) -> Bool.False
3218 | DJNZ (x, x0) -> Bool.False
3219 | ANL x -> Bool.False
3220 | ORL x -> Bool.False
3221 | XRL x -> Bool.False
3222 | CLR x -> Bool.False
3223 | CPL x -> Bool.False
3224 | RL x -> Bool.False
3225 | RLC x -> Bool.False
3226 | RR x -> Bool.False
3227 | RRC x -> Bool.False
3228 | SWAP x -> Bool.False
3229 | MOV x -> Bool.False
3230 | MOVX x -> Bool.False
3231 | SETB x -> Bool.False
3232 | PUSH x -> Bool.False
3233 | POP x -> Bool.False
3234 | XCH (x, x0) -> Bool.False
3235 | XCHD (x, x0) -> Bool.False
3237 | RETI -> Bool.False
3239 | JMP x -> Bool.False)
3242 | ADD (x, x0) -> Bool.False
3243 | ADDC (x, x0) -> Bool.False
3244 | SUBB (x, x0) -> Bool.False
3245 | INC x -> Bool.False
3248 (subaddressing_modeel (Nat.S (Nat.S (Nat.S Nat.O))) (Vector.VCons
3249 ((Nat.S (Nat.S (Nat.S Nat.O))), Acc_a, (Vector.VCons ((Nat.S
3250 (Nat.S Nat.O)), Registr, (Vector.VCons ((Nat.S Nat.O), Direct,
3251 (Vector.VCons (Nat.O, Indirect, Vector.VEmpty)))))))) arg)
3252 (subaddressing_modeel (Nat.S (Nat.S (Nat.S Nat.O))) (Vector.VCons
3253 ((Nat.S (Nat.S (Nat.S Nat.O))), Acc_a, (Vector.VCons ((Nat.S
3254 (Nat.S Nat.O)), Registr, (Vector.VCons ((Nat.S Nat.O), Direct,
3255 (Vector.VCons (Nat.O, Indirect, Vector.VEmpty)))))))) arg')
3256 | MUL (x, x0) -> Bool.False
3257 | DIV (x, x0) -> Bool.False
3258 | DA x -> Bool.False
3259 | JC x -> Bool.False
3260 | JNC x -> Bool.False
3261 | JB (x, x0) -> Bool.False
3262 | JNB (x, x0) -> Bool.False
3263 | JBC (x, x0) -> Bool.False
3264 | JZ x -> Bool.False
3265 | JNZ x -> Bool.False
3266 | CJNE (x, x0) -> Bool.False
3267 | DJNZ (x, x0) -> Bool.False
3268 | ANL x -> Bool.False
3269 | ORL x -> Bool.False
3270 | XRL x -> Bool.False
3271 | CLR x -> Bool.False
3272 | CPL x -> Bool.False
3273 | RL x -> Bool.False
3274 | RLC x -> Bool.False
3275 | RR x -> Bool.False
3276 | RRC x -> Bool.False
3277 | SWAP x -> Bool.False
3278 | MOV x -> Bool.False
3279 | MOVX x -> Bool.False
3280 | SETB x -> Bool.False
3281 | PUSH x -> Bool.False
3282 | POP x -> Bool.False
3283 | XCH (x, x0) -> Bool.False
3284 | XCHD (x, x0) -> Bool.False
3286 | RETI -> Bool.False
3288 | JMP x -> Bool.False)
3289 | MUL (arg1, arg2) ->
3291 | ADD (x, x0) -> Bool.False
3292 | ADDC (x, x0) -> Bool.False
3293 | SUBB (x, x0) -> Bool.False
3294 | INC x -> Bool.False
3295 | DEC x -> Bool.False
3296 | MUL (arg1', arg2') ->
3299 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
3300 Vector.VEmpty)) arg1)
3301 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
3302 Vector.VEmpty)) arg1'))
3304 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_b,
3305 Vector.VEmpty)) arg2)
3306 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_b,
3307 Vector.VEmpty)) arg2'))
3308 | DIV (x, x0) -> Bool.False
3309 | DA x -> Bool.False
3310 | JC x -> Bool.False
3311 | JNC x -> Bool.False
3312 | JB (x, x0) -> Bool.False
3313 | JNB (x, x0) -> Bool.False
3314 | JBC (x, x0) -> Bool.False
3315 | JZ x -> Bool.False
3316 | JNZ x -> Bool.False
3317 | CJNE (x, x0) -> Bool.False
3318 | DJNZ (x, x0) -> Bool.False
3319 | ANL x -> Bool.False
3320 | ORL x -> Bool.False
3321 | XRL x -> Bool.False
3322 | CLR x -> Bool.False
3323 | CPL x -> Bool.False
3324 | RL x -> Bool.False
3325 | RLC x -> Bool.False
3326 | RR x -> Bool.False
3327 | RRC x -> Bool.False
3328 | SWAP x -> Bool.False
3329 | MOV x -> Bool.False
3330 | MOVX x -> Bool.False
3331 | SETB x -> Bool.False
3332 | PUSH x -> Bool.False
3333 | POP x -> Bool.False
3334 | XCH (x, x0) -> Bool.False
3335 | XCHD (x, x0) -> Bool.False
3337 | RETI -> Bool.False
3339 | JMP x -> Bool.False)
3340 | DIV (arg1, arg2) ->
3342 | ADD (x, x0) -> Bool.False
3343 | ADDC (x, x0) -> Bool.False
3344 | SUBB (x, x0) -> Bool.False
3345 | INC x -> Bool.False
3346 | DEC x -> Bool.False
3347 | MUL (x, x0) -> Bool.False
3348 | DIV (arg1', arg2') ->
3351 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
3352 Vector.VEmpty)) arg1)
3353 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
3354 Vector.VEmpty)) arg1'))
3356 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_b,
3357 Vector.VEmpty)) arg2)
3358 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_b,
3359 Vector.VEmpty)) arg2'))
3360 | DA x -> Bool.False
3361 | JC x -> Bool.False
3362 | JNC x -> Bool.False
3363 | JB (x, x0) -> Bool.False
3364 | JNB (x, x0) -> Bool.False
3365 | JBC (x, x0) -> Bool.False
3366 | JZ x -> Bool.False
3367 | JNZ x -> Bool.False
3368 | CJNE (x, x0) -> Bool.False
3369 | DJNZ (x, x0) -> Bool.False
3370 | ANL x -> Bool.False
3371 | ORL x -> Bool.False
3372 | XRL x -> Bool.False
3373 | CLR x -> Bool.False
3374 | CPL x -> Bool.False
3375 | RL x -> Bool.False
3376 | RLC x -> Bool.False
3377 | RR x -> Bool.False
3378 | RRC x -> Bool.False
3379 | SWAP x -> Bool.False
3380 | MOV x -> Bool.False
3381 | MOVX x -> Bool.False
3382 | SETB x -> Bool.False
3383 | PUSH x -> Bool.False
3384 | POP x -> Bool.False
3385 | XCH (x, x0) -> Bool.False
3386 | XCHD (x, x0) -> Bool.False
3388 | RETI -> Bool.False
3390 | JMP x -> Bool.False)
3393 | ADD (x, x0) -> Bool.False
3394 | ADDC (x, x0) -> Bool.False
3395 | SUBB (x, x0) -> Bool.False
3396 | INC x -> Bool.False
3397 | DEC x -> Bool.False
3398 | MUL (x, x0) -> Bool.False
3399 | DIV (x, x0) -> Bool.False
3402 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
3403 Vector.VEmpty)) arg)
3404 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
3405 Vector.VEmpty)) arg')
3406 | JC x -> Bool.False
3407 | JNC x -> Bool.False
3408 | JB (x, x0) -> Bool.False
3409 | JNB (x, x0) -> Bool.False
3410 | JBC (x, x0) -> Bool.False
3411 | JZ x -> Bool.False
3412 | JNZ x -> Bool.False
3413 | CJNE (x, x0) -> Bool.False
3414 | DJNZ (x, x0) -> Bool.False
3415 | ANL x -> Bool.False
3416 | ORL x -> Bool.False
3417 | XRL x -> Bool.False
3418 | CLR x -> Bool.False
3419 | CPL x -> Bool.False
3420 | RL x -> Bool.False
3421 | RLC x -> Bool.False
3422 | RR x -> Bool.False
3423 | RRC x -> Bool.False
3424 | SWAP x -> Bool.False
3425 | MOV x -> Bool.False
3426 | MOVX x -> Bool.False
3427 | SETB x -> Bool.False
3428 | PUSH x -> Bool.False
3429 | POP x -> Bool.False
3430 | XCH (x, x0) -> Bool.False
3431 | XCHD (x, x0) -> Bool.False
3433 | RETI -> Bool.False
3435 | JMP x -> Bool.False)
3438 | ADD (x, x0) -> Bool.False
3439 | ADDC (x, x0) -> Bool.False
3440 | SUBB (x, x0) -> Bool.False
3441 | INC x -> Bool.False
3442 | DEC x -> Bool.False
3443 | MUL (x, x0) -> Bool.False
3444 | DIV (x, x0) -> Bool.False
3445 | DA x -> Bool.False
3448 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Relative,
3449 Vector.VEmpty)) arg)
3450 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Relative,
3451 Vector.VEmpty)) arg')
3452 | JNC x -> Bool.False
3453 | JB (x, x0) -> Bool.False
3454 | JNB (x, x0) -> Bool.False
3455 | JBC (x, x0) -> Bool.False
3456 | JZ x -> Bool.False
3457 | JNZ x -> Bool.False
3458 | CJNE (x, x0) -> Bool.False
3459 | DJNZ (x, x0) -> Bool.False
3460 | ANL x -> Bool.False
3461 | ORL x -> Bool.False
3462 | XRL x -> Bool.False
3463 | CLR x -> Bool.False
3464 | CPL x -> Bool.False
3465 | RL x -> Bool.False
3466 | RLC x -> Bool.False
3467 | RR x -> Bool.False
3468 | RRC x -> Bool.False
3469 | SWAP x -> Bool.False
3470 | MOV x -> Bool.False
3471 | MOVX x -> Bool.False
3472 | SETB x -> Bool.False
3473 | PUSH x -> Bool.False
3474 | POP x -> Bool.False
3475 | XCH (x, x0) -> Bool.False
3476 | XCHD (x, x0) -> Bool.False
3478 | RETI -> Bool.False
3480 | JMP x -> Bool.False)
3483 | ADD (x, x0) -> Bool.False
3484 | ADDC (x, x0) -> Bool.False
3485 | SUBB (x, x0) -> Bool.False
3486 | INC x -> Bool.False
3487 | DEC x -> Bool.False
3488 | MUL (x, x0) -> Bool.False
3489 | DIV (x, x0) -> Bool.False
3490 | DA x -> Bool.False
3491 | JC x -> Bool.False
3494 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Relative,
3495 Vector.VEmpty)) arg)
3496 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Relative,
3497 Vector.VEmpty)) arg')
3498 | JB (x, x0) -> Bool.False
3499 | JNB (x, x0) -> Bool.False
3500 | JBC (x, x0) -> Bool.False
3501 | JZ x -> Bool.False
3502 | JNZ x -> Bool.False
3503 | CJNE (x, x0) -> Bool.False
3504 | DJNZ (x, x0) -> Bool.False
3505 | ANL x -> Bool.False
3506 | ORL x -> Bool.False
3507 | XRL x -> Bool.False
3508 | CLR x -> Bool.False
3509 | CPL x -> Bool.False
3510 | RL x -> Bool.False
3511 | RLC x -> Bool.False
3512 | RR x -> Bool.False
3513 | RRC x -> Bool.False
3514 | SWAP x -> Bool.False
3515 | MOV x -> Bool.False
3516 | MOVX x -> Bool.False
3517 | SETB x -> Bool.False
3518 | PUSH x -> Bool.False
3519 | POP x -> Bool.False
3520 | XCH (x, x0) -> Bool.False
3521 | XCHD (x, x0) -> Bool.False
3523 | RETI -> Bool.False
3525 | JMP x -> Bool.False)
3526 | JB (arg1, arg2) ->
3528 | ADD (x, x0) -> Bool.False
3529 | ADDC (x, x0) -> Bool.False
3530 | SUBB (x, x0) -> Bool.False
3531 | INC x -> Bool.False
3532 | DEC x -> Bool.False
3533 | MUL (x, x0) -> Bool.False
3534 | DIV (x, x0) -> Bool.False
3535 | DA x -> Bool.False
3536 | JC x -> Bool.False
3537 | JNC x -> Bool.False
3538 | JB (arg1', arg2') ->
3541 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Bit_addr,
3542 Vector.VEmpty)) arg1)
3543 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Bit_addr,
3544 Vector.VEmpty)) arg1'))
3546 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Relative,
3547 Vector.VEmpty)) arg2)
3548 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Relative,
3549 Vector.VEmpty)) arg2'))
3550 | JNB (x, x0) -> Bool.False
3551 | JBC (x, x0) -> Bool.False
3552 | JZ x -> Bool.False
3553 | JNZ x -> Bool.False
3554 | CJNE (x, x0) -> Bool.False
3555 | DJNZ (x, x0) -> Bool.False
3556 | ANL x -> Bool.False
3557 | ORL x -> Bool.False
3558 | XRL x -> Bool.False
3559 | CLR x -> Bool.False
3560 | CPL x -> Bool.False
3561 | RL x -> Bool.False
3562 | RLC x -> Bool.False
3563 | RR x -> Bool.False
3564 | RRC x -> Bool.False
3565 | SWAP x -> Bool.False
3566 | MOV x -> Bool.False
3567 | MOVX x -> Bool.False
3568 | SETB x -> Bool.False
3569 | PUSH x -> Bool.False
3570 | POP x -> Bool.False
3571 | XCH (x, x0) -> Bool.False
3572 | XCHD (x, x0) -> Bool.False
3574 | RETI -> Bool.False
3576 | JMP x -> Bool.False)
3577 | JNB (arg1, arg2) ->
3579 | ADD (x, x0) -> Bool.False
3580 | ADDC (x, x0) -> Bool.False
3581 | SUBB (x, x0) -> Bool.False
3582 | INC x -> Bool.False
3583 | DEC x -> Bool.False
3584 | MUL (x, x0) -> Bool.False
3585 | DIV (x, x0) -> Bool.False
3586 | DA x -> Bool.False
3587 | JC x -> Bool.False
3588 | JNC x -> Bool.False
3589 | JB (x, x0) -> Bool.False
3590 | JNB (arg1', arg2') ->
3593 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Bit_addr,
3594 Vector.VEmpty)) arg1)
3595 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Bit_addr,
3596 Vector.VEmpty)) arg1'))
3598 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Relative,
3599 Vector.VEmpty)) arg2)
3600 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Relative,
3601 Vector.VEmpty)) arg2'))
3602 | JBC (x, x0) -> Bool.False
3603 | JZ x -> Bool.False
3604 | JNZ x -> Bool.False
3605 | CJNE (x, x0) -> Bool.False
3606 | DJNZ (x, x0) -> Bool.False
3607 | ANL x -> Bool.False
3608 | ORL x -> Bool.False
3609 | XRL x -> Bool.False
3610 | CLR x -> Bool.False
3611 | CPL x -> Bool.False
3612 | RL x -> Bool.False
3613 | RLC x -> Bool.False
3614 | RR x -> Bool.False
3615 | RRC x -> Bool.False
3616 | SWAP x -> Bool.False
3617 | MOV x -> Bool.False
3618 | MOVX x -> Bool.False
3619 | SETB x -> Bool.False
3620 | PUSH x -> Bool.False
3621 | POP x -> Bool.False
3622 | XCH (x, x0) -> Bool.False
3623 | XCHD (x, x0) -> Bool.False
3625 | RETI -> Bool.False
3627 | JMP x -> Bool.False)
3628 | JBC (arg1, arg2) ->
3630 | ADD (x, x0) -> Bool.False
3631 | ADDC (x, x0) -> Bool.False
3632 | SUBB (x, x0) -> Bool.False
3633 | INC x -> Bool.False
3634 | DEC x -> Bool.False
3635 | MUL (x, x0) -> Bool.False
3636 | DIV (x, x0) -> Bool.False
3637 | DA x -> Bool.False
3638 | JC x -> Bool.False
3639 | JNC x -> Bool.False
3640 | JB (x, x0) -> Bool.False
3641 | JNB (x, x0) -> Bool.False
3642 | JBC (arg1', arg2') ->
3645 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Bit_addr,
3646 Vector.VEmpty)) arg1)
3647 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Bit_addr,
3648 Vector.VEmpty)) arg1'))
3650 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Relative,
3651 Vector.VEmpty)) arg2)
3652 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Relative,
3653 Vector.VEmpty)) arg2'))
3654 | JZ x -> Bool.False
3655 | JNZ x -> Bool.False
3656 | CJNE (x, x0) -> Bool.False
3657 | DJNZ (x, x0) -> Bool.False
3658 | ANL x -> Bool.False
3659 | ORL x -> Bool.False
3660 | XRL x -> Bool.False
3661 | CLR x -> Bool.False
3662 | CPL x -> Bool.False
3663 | RL x -> Bool.False
3664 | RLC x -> Bool.False
3665 | RR x -> Bool.False
3666 | RRC x -> Bool.False
3667 | SWAP x -> Bool.False
3668 | MOV x -> Bool.False
3669 | MOVX x -> Bool.False
3670 | SETB x -> Bool.False
3671 | PUSH x -> Bool.False
3672 | POP x -> Bool.False
3673 | XCH (x, x0) -> Bool.False
3674 | XCHD (x, x0) -> Bool.False
3676 | RETI -> Bool.False
3678 | JMP x -> Bool.False)
3681 | ADD (x, x0) -> Bool.False
3682 | ADDC (x, x0) -> Bool.False
3683 | SUBB (x, x0) -> Bool.False
3684 | INC x -> Bool.False
3685 | DEC x -> Bool.False
3686 | MUL (x, x0) -> Bool.False
3687 | DIV (x, x0) -> Bool.False
3688 | DA x -> Bool.False
3689 | JC x -> Bool.False
3690 | JNC x -> Bool.False
3691 | JB (x, x0) -> Bool.False
3692 | JNB (x, x0) -> Bool.False
3693 | JBC (x, x0) -> Bool.False
3696 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Relative,
3697 Vector.VEmpty)) arg)
3698 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Relative,
3699 Vector.VEmpty)) arg')
3700 | JNZ x -> Bool.False
3701 | CJNE (x, x0) -> Bool.False
3702 | DJNZ (x, x0) -> Bool.False
3703 | ANL x -> Bool.False
3704 | ORL x -> Bool.False
3705 | XRL x -> Bool.False
3706 | CLR x -> Bool.False
3707 | CPL x -> Bool.False
3708 | RL x -> Bool.False
3709 | RLC x -> Bool.False
3710 | RR x -> Bool.False
3711 | RRC x -> Bool.False
3712 | SWAP x -> Bool.False
3713 | MOV x -> Bool.False
3714 | MOVX x -> Bool.False
3715 | SETB x -> Bool.False
3716 | PUSH x -> Bool.False
3717 | POP x -> Bool.False
3718 | XCH (x, x0) -> Bool.False
3719 | XCHD (x, x0) -> Bool.False
3721 | RETI -> Bool.False
3723 | JMP x -> Bool.False)
3726 | ADD (x, x0) -> Bool.False
3727 | ADDC (x, x0) -> Bool.False
3728 | SUBB (x, x0) -> Bool.False
3729 | INC x -> Bool.False
3730 | DEC x -> Bool.False
3731 | MUL (x, x0) -> Bool.False
3732 | DIV (x, x0) -> Bool.False
3733 | DA x -> Bool.False
3734 | JC x -> Bool.False
3735 | JNC x -> Bool.False
3736 | JB (x, x0) -> Bool.False
3737 | JNB (x, x0) -> Bool.False
3738 | JBC (x, x0) -> Bool.False
3739 | JZ x -> Bool.False
3742 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Relative,
3743 Vector.VEmpty)) arg)
3744 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Relative,
3745 Vector.VEmpty)) arg')
3746 | CJNE (x, x0) -> Bool.False
3747 | DJNZ (x, x0) -> Bool.False
3748 | ANL x -> Bool.False
3749 | ORL x -> Bool.False
3750 | XRL x -> Bool.False
3751 | CLR x -> Bool.False
3752 | CPL x -> Bool.False
3753 | RL x -> Bool.False
3754 | RLC x -> Bool.False
3755 | RR x -> Bool.False
3756 | RRC x -> Bool.False
3757 | SWAP x -> Bool.False
3758 | MOV x -> Bool.False
3759 | MOVX x -> Bool.False
3760 | SETB x -> Bool.False
3761 | PUSH x -> Bool.False
3762 | POP x -> Bool.False
3763 | XCH (x, x0) -> Bool.False
3764 | XCHD (x, x0) -> Bool.False
3766 | RETI -> Bool.False
3768 | JMP x -> Bool.False)
3769 | CJNE (arg1, arg2) ->
3771 | ADD (x, x0) -> Bool.False
3772 | ADDC (x, x0) -> Bool.False
3773 | SUBB (x, x0) -> Bool.False
3774 | INC x -> Bool.False
3775 | DEC x -> Bool.False
3776 | MUL (x, x0) -> Bool.False
3777 | DIV (x, x0) -> Bool.False
3778 | DA x -> Bool.False
3779 | JC x -> Bool.False
3780 | JNC x -> Bool.False
3781 | JB (x, x0) -> Bool.False
3782 | JNB (x, x0) -> Bool.False
3783 | JBC (x, x0) -> Bool.False
3784 | JZ x -> Bool.False
3785 | JNZ x -> Bool.False
3786 | CJNE (arg1', arg2') ->
3788 Util.eq_prod (fun h h1 ->
3790 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
3792 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
3793 Vector.VEmpty)) h1)) (fun h h1 ->
3795 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S
3796 Nat.O), Direct, (Vector.VCons (Nat.O, Data, Vector.VEmpty))))
3798 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S
3799 Nat.O), Direct, (Vector.VCons (Nat.O, Data, Vector.VEmpty))))
3803 Util.eq_prod (fun h h1 ->
3805 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S
3806 Nat.O), Registr, (Vector.VCons (Nat.O, Indirect,
3807 Vector.VEmpty)))) h)
3808 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S
3809 Nat.O), Registr, (Vector.VCons (Nat.O, Indirect,
3810 Vector.VEmpty)))) h1)) (fun h h1 ->
3812 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Data,
3814 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Data,
3815 Vector.VEmpty)) h1))
3817 let arg1_eq = Util.eq_sum prod_eq_left prod_eq_right in
3818 Bool.andb (arg1_eq arg1 arg1')
3820 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Relative,
3821 Vector.VEmpty)) arg2)
3822 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Relative,
3823 Vector.VEmpty)) arg2'))
3824 | DJNZ (x, x0) -> Bool.False
3825 | ANL x -> Bool.False
3826 | ORL x -> Bool.False
3827 | XRL x -> Bool.False
3828 | CLR x -> Bool.False
3829 | CPL x -> Bool.False
3830 | RL x -> Bool.False
3831 | RLC x -> Bool.False
3832 | RR x -> Bool.False
3833 | RRC x -> Bool.False
3834 | SWAP x -> Bool.False
3835 | MOV x -> Bool.False
3836 | MOVX x -> Bool.False
3837 | SETB x -> Bool.False
3838 | PUSH x -> Bool.False
3839 | POP x -> Bool.False
3840 | XCH (x, x0) -> Bool.False
3841 | XCHD (x, x0) -> Bool.False
3843 | RETI -> Bool.False
3845 | JMP x -> Bool.False)
3846 | DJNZ (arg1, arg2) ->
3848 | ADD (x, x0) -> Bool.False
3849 | ADDC (x, x0) -> Bool.False
3850 | SUBB (x, x0) -> Bool.False
3851 | INC x -> Bool.False
3852 | DEC x -> Bool.False
3853 | MUL (x, x0) -> Bool.False
3854 | DIV (x, x0) -> Bool.False
3855 | DA x -> Bool.False
3856 | JC x -> Bool.False
3857 | JNC x -> Bool.False
3858 | JB (x, x0) -> Bool.False
3859 | JNB (x, x0) -> Bool.False
3860 | JBC (x, x0) -> Bool.False
3861 | JZ x -> Bool.False
3862 | JNZ x -> Bool.False
3863 | CJNE (x, x0) -> Bool.False
3864 | DJNZ (arg1', arg2') ->
3867 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S Nat.O),
3868 Registr, (Vector.VCons (Nat.O, Direct, Vector.VEmpty)))) arg1)
3869 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S Nat.O),
3870 Registr, (Vector.VCons (Nat.O, Direct, Vector.VEmpty)))) arg1'))
3872 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Relative,
3873 Vector.VEmpty)) arg2)
3874 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Relative,
3875 Vector.VEmpty)) arg2'))
3876 | ANL x -> Bool.False
3877 | ORL x -> Bool.False
3878 | XRL x -> Bool.False
3879 | CLR x -> Bool.False
3880 | CPL x -> Bool.False
3881 | RL x -> Bool.False
3882 | RLC x -> Bool.False
3883 | RR x -> Bool.False
3884 | RRC x -> Bool.False
3885 | SWAP x -> Bool.False
3886 | MOV x -> Bool.False
3887 | MOVX x -> Bool.False
3888 | SETB x -> Bool.False
3889 | PUSH x -> Bool.False
3890 | POP x -> Bool.False
3891 | XCH (x, x0) -> Bool.False
3892 | XCHD (x, x0) -> Bool.False
3894 | RETI -> Bool.False
3896 | JMP x -> Bool.False)
3899 | ADD (x, x0) -> Bool.False
3900 | ADDC (x, x0) -> Bool.False
3901 | SUBB (x, x0) -> Bool.False
3902 | INC x -> Bool.False
3903 | DEC x -> Bool.False
3904 | MUL (x, x0) -> Bool.False
3905 | DIV (x, x0) -> Bool.False
3906 | DA x -> Bool.False
3907 | JC x -> Bool.False
3908 | JNC x -> Bool.False
3909 | JB (x, x0) -> Bool.False
3910 | JNB (x, x0) -> Bool.False
3911 | JBC (x, x0) -> Bool.False
3912 | JZ x -> Bool.False
3913 | JNZ x -> Bool.False
3914 | CJNE (x, x0) -> Bool.False
3915 | DJNZ (x, x0) -> Bool.False
3918 Util.eq_prod (fun h h1 ->
3920 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
3922 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
3923 Vector.VEmpty)) h1)) (fun h h1 ->
3925 (subaddressing_modeel (Nat.S (Nat.S (Nat.S Nat.O)))
3926 (Vector.VCons ((Nat.S (Nat.S (Nat.S Nat.O))), Registr,
3927 (Vector.VCons ((Nat.S (Nat.S Nat.O)), Direct, (Vector.VCons
3928 ((Nat.S Nat.O), Indirect, (Vector.VCons (Nat.O, Data,
3929 Vector.VEmpty)))))))) h)
3930 (subaddressing_modeel (Nat.S (Nat.S (Nat.S Nat.O)))
3931 (Vector.VCons ((Nat.S (Nat.S (Nat.S Nat.O))), Registr,
3932 (Vector.VCons ((Nat.S (Nat.S Nat.O)), Direct, (Vector.VCons
3933 ((Nat.S Nat.O), Indirect, (Vector.VCons (Nat.O, Data,
3934 Vector.VEmpty)))))))) h1))
3937 Util.eq_prod (fun h h1 ->
3939 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Direct,
3941 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Direct,
3942 Vector.VEmpty)) h1)) (fun h h1 ->
3944 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S
3945 Nat.O), Acc_a, (Vector.VCons (Nat.O, Data, Vector.VEmpty))))
3947 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S
3948 Nat.O), Acc_a, (Vector.VCons (Nat.O, Data, Vector.VEmpty))))
3951 let prod_eq_left = Util.eq_sum prod_eq_left1 prod_eq_left2 in
3953 Util.eq_prod (fun h h1 ->
3955 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Carry,
3957 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Carry,
3958 Vector.VEmpty)) h1)) (fun h h1 ->
3960 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S
3961 Nat.O), Bit_addr, (Vector.VCons (Nat.O, N_bit_addr,
3962 Vector.VEmpty)))) h)
3963 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S
3964 Nat.O), Bit_addr, (Vector.VCons (Nat.O, N_bit_addr,
3965 Vector.VEmpty)))) h1))
3967 let sum_eq = Util.eq_sum prod_eq_left prod_eq_right in sum_eq arg arg'
3968 | ORL x -> Bool.False
3969 | XRL x -> Bool.False
3970 | CLR x -> Bool.False
3971 | CPL x -> Bool.False
3972 | RL x -> Bool.False
3973 | RLC x -> Bool.False
3974 | RR x -> Bool.False
3975 | RRC x -> Bool.False
3976 | SWAP x -> Bool.False
3977 | MOV x -> Bool.False
3978 | MOVX x -> Bool.False
3979 | SETB x -> Bool.False
3980 | PUSH x -> Bool.False
3981 | POP x -> Bool.False
3982 | XCH (x, x0) -> Bool.False
3983 | XCHD (x, x0) -> Bool.False
3985 | RETI -> Bool.False
3987 | JMP x -> Bool.False)
3990 | ADD (x, x0) -> Bool.False
3991 | ADDC (x, x0) -> Bool.False
3992 | SUBB (x, x0) -> Bool.False
3993 | INC x -> Bool.False
3994 | DEC x -> Bool.False
3995 | MUL (x, x0) -> Bool.False
3996 | DIV (x, x0) -> Bool.False
3997 | DA x -> Bool.False
3998 | JC x -> Bool.False
3999 | JNC x -> Bool.False
4000 | JB (x, x0) -> Bool.False
4001 | JNB (x, x0) -> Bool.False
4002 | JBC (x, x0) -> Bool.False
4003 | JZ x -> Bool.False
4004 | JNZ x -> Bool.False
4005 | CJNE (x, x0) -> Bool.False
4006 | DJNZ (x, x0) -> Bool.False
4007 | ANL x -> Bool.False
4010 Util.eq_prod (fun h h1 ->
4012 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4014 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4015 Vector.VEmpty)) h1)) (fun h h1 ->
4017 (subaddressing_modeel (Nat.S (Nat.S (Nat.S Nat.O)))
4018 (Vector.VCons ((Nat.S (Nat.S (Nat.S Nat.O))), Registr,
4019 (Vector.VCons ((Nat.S (Nat.S Nat.O)), Data, (Vector.VCons
4020 ((Nat.S Nat.O), Direct, (Vector.VCons (Nat.O, Indirect,
4021 Vector.VEmpty)))))))) h)
4022 (subaddressing_modeel (Nat.S (Nat.S (Nat.S Nat.O)))
4023 (Vector.VCons ((Nat.S (Nat.S (Nat.S Nat.O))), Registr,
4024 (Vector.VCons ((Nat.S (Nat.S Nat.O)), Data, (Vector.VCons
4025 ((Nat.S Nat.O), Direct, (Vector.VCons (Nat.O, Indirect,
4026 Vector.VEmpty)))))))) h1))
4029 Util.eq_prod (fun h h1 ->
4031 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Direct,
4033 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Direct,
4034 Vector.VEmpty)) h1)) (fun h h1 ->
4036 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S
4037 Nat.O), Acc_a, (Vector.VCons (Nat.O, Data, Vector.VEmpty))))
4039 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S
4040 Nat.O), Acc_a, (Vector.VCons (Nat.O, Data, Vector.VEmpty))))
4043 let prod_eq_left = Util.eq_sum prod_eq_left1 prod_eq_left2 in
4045 Util.eq_prod (fun h h1 ->
4047 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Carry,
4049 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Carry,
4050 Vector.VEmpty)) h1)) (fun h h1 ->
4052 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S
4053 Nat.O), Bit_addr, (Vector.VCons (Nat.O, N_bit_addr,
4054 Vector.VEmpty)))) h)
4055 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S
4056 Nat.O), Bit_addr, (Vector.VCons (Nat.O, N_bit_addr,
4057 Vector.VEmpty)))) h1))
4059 let sum_eq = Util.eq_sum prod_eq_left prod_eq_right in sum_eq arg arg'
4060 | XRL x -> Bool.False
4061 | CLR x -> Bool.False
4062 | CPL x -> Bool.False
4063 | RL x -> Bool.False
4064 | RLC x -> Bool.False
4065 | RR x -> Bool.False
4066 | RRC x -> Bool.False
4067 | SWAP x -> Bool.False
4068 | MOV x -> Bool.False
4069 | MOVX x -> Bool.False
4070 | SETB x -> Bool.False
4071 | PUSH x -> Bool.False
4072 | POP x -> Bool.False
4073 | XCH (x, x0) -> Bool.False
4074 | XCHD (x, x0) -> Bool.False
4076 | RETI -> Bool.False
4078 | JMP x -> Bool.False)
4081 | ADD (x, x0) -> Bool.False
4082 | ADDC (x, x0) -> Bool.False
4083 | SUBB (x, x0) -> Bool.False
4084 | INC x -> Bool.False
4085 | DEC x -> Bool.False
4086 | MUL (x, x0) -> Bool.False
4087 | DIV (x, x0) -> Bool.False
4088 | DA x -> Bool.False
4089 | JC x -> Bool.False
4090 | JNC x -> Bool.False
4091 | JB (x, x0) -> Bool.False
4092 | JNB (x, x0) -> Bool.False
4093 | JBC (x, x0) -> Bool.False
4094 | JZ x -> Bool.False
4095 | JNZ x -> Bool.False
4096 | CJNE (x, x0) -> Bool.False
4097 | DJNZ (x, x0) -> Bool.False
4098 | ANL x -> Bool.False
4099 | ORL x -> Bool.False
4102 Util.eq_prod (fun h h1 ->
4104 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4106 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4107 Vector.VEmpty)) h1)) (fun h h1 ->
4109 (subaddressing_modeel (Nat.S (Nat.S (Nat.S Nat.O)))
4110 (Vector.VCons ((Nat.S (Nat.S (Nat.S Nat.O))), Data,
4111 (Vector.VCons ((Nat.S (Nat.S Nat.O)), Registr, (Vector.VCons
4112 ((Nat.S Nat.O), Direct, (Vector.VCons (Nat.O, Indirect,
4113 Vector.VEmpty)))))))) h)
4114 (subaddressing_modeel (Nat.S (Nat.S (Nat.S Nat.O)))
4115 (Vector.VCons ((Nat.S (Nat.S (Nat.S Nat.O))), Data,
4116 (Vector.VCons ((Nat.S (Nat.S Nat.O)), Registr, (Vector.VCons
4117 ((Nat.S Nat.O), Direct, (Vector.VCons (Nat.O, Indirect,
4118 Vector.VEmpty)))))))) h1))
4121 Util.eq_prod (fun h h1 ->
4123 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Direct,
4125 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Direct,
4126 Vector.VEmpty)) h1)) (fun h h1 ->
4128 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S
4129 Nat.O), Acc_a, (Vector.VCons (Nat.O, Data, Vector.VEmpty))))
4131 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S
4132 Nat.O), Acc_a, (Vector.VCons (Nat.O, Data, Vector.VEmpty))))
4135 let sum_eq = Util.eq_sum prod_eq_left prod_eq_right in sum_eq arg arg'
4136 | CLR x -> Bool.False
4137 | CPL x -> Bool.False
4138 | RL x -> Bool.False
4139 | RLC x -> Bool.False
4140 | RR x -> Bool.False
4141 | RRC x -> Bool.False
4142 | SWAP x -> Bool.False
4143 | MOV x -> Bool.False
4144 | MOVX x -> Bool.False
4145 | SETB x -> Bool.False
4146 | PUSH x -> Bool.False
4147 | POP x -> Bool.False
4148 | XCH (x, x0) -> Bool.False
4149 | XCHD (x, x0) -> Bool.False
4151 | RETI -> Bool.False
4153 | JMP x -> Bool.False)
4156 | ADD (x, x0) -> Bool.False
4157 | ADDC (x, x0) -> Bool.False
4158 | SUBB (x, x0) -> Bool.False
4159 | INC x -> Bool.False
4160 | DEC x -> Bool.False
4161 | MUL (x, x0) -> Bool.False
4162 | DIV (x, x0) -> Bool.False
4163 | DA x -> Bool.False
4164 | JC x -> Bool.False
4165 | JNC x -> Bool.False
4166 | JB (x, x0) -> Bool.False
4167 | JNB (x, x0) -> Bool.False
4168 | JBC (x, x0) -> Bool.False
4169 | JZ x -> Bool.False
4170 | JNZ x -> Bool.False
4171 | CJNE (x, x0) -> Bool.False
4172 | DJNZ (x, x0) -> Bool.False
4173 | ANL x -> Bool.False
4174 | ORL x -> Bool.False
4175 | XRL x -> Bool.False
4178 (subaddressing_modeel (Nat.S (Nat.S Nat.O)) (Vector.VCons ((Nat.S
4179 (Nat.S Nat.O)), Acc_a, (Vector.VCons ((Nat.S Nat.O), Carry,
4180 (Vector.VCons (Nat.O, Bit_addr, Vector.VEmpty)))))) arg)
4181 (subaddressing_modeel (Nat.S (Nat.S Nat.O)) (Vector.VCons ((Nat.S
4182 (Nat.S Nat.O)), Acc_a, (Vector.VCons ((Nat.S Nat.O), Carry,
4183 (Vector.VCons (Nat.O, Bit_addr, Vector.VEmpty)))))) arg')
4184 | CPL x -> Bool.False
4185 | RL x -> Bool.False
4186 | RLC x -> Bool.False
4187 | RR x -> Bool.False
4188 | RRC x -> Bool.False
4189 | SWAP x -> Bool.False
4190 | MOV x -> Bool.False
4191 | MOVX x -> Bool.False
4192 | SETB x -> Bool.False
4193 | PUSH x -> Bool.False
4194 | POP x -> Bool.False
4195 | XCH (x, x0) -> Bool.False
4196 | XCHD (x, x0) -> Bool.False
4198 | RETI -> Bool.False
4200 | JMP x -> Bool.False)
4203 | ADD (x, x0) -> Bool.False
4204 | ADDC (x, x0) -> Bool.False
4205 | SUBB (x, x0) -> Bool.False
4206 | INC x -> Bool.False
4207 | DEC x -> Bool.False
4208 | MUL (x, x0) -> Bool.False
4209 | DIV (x, x0) -> Bool.False
4210 | DA x -> Bool.False
4211 | JC x -> Bool.False
4212 | JNC x -> Bool.False
4213 | JB (x, x0) -> Bool.False
4214 | JNB (x, x0) -> Bool.False
4215 | JBC (x, x0) -> Bool.False
4216 | JZ x -> Bool.False
4217 | JNZ x -> Bool.False
4218 | CJNE (x, x0) -> Bool.False
4219 | DJNZ (x, x0) -> Bool.False
4220 | ANL x -> Bool.False
4221 | ORL x -> Bool.False
4222 | XRL x -> Bool.False
4223 | CLR x -> Bool.False
4226 (subaddressing_modeel (Nat.S (Nat.S Nat.O)) (Vector.VCons ((Nat.S
4227 (Nat.S Nat.O)), Acc_a, (Vector.VCons ((Nat.S Nat.O), Carry,
4228 (Vector.VCons (Nat.O, Bit_addr, Vector.VEmpty)))))) arg)
4229 (subaddressing_modeel (Nat.S (Nat.S Nat.O)) (Vector.VCons ((Nat.S
4230 (Nat.S Nat.O)), Acc_a, (Vector.VCons ((Nat.S Nat.O), Carry,
4231 (Vector.VCons (Nat.O, Bit_addr, Vector.VEmpty)))))) arg')
4232 | RL x -> Bool.False
4233 | RLC x -> Bool.False
4234 | RR x -> Bool.False
4235 | RRC x -> Bool.False
4236 | SWAP x -> Bool.False
4237 | MOV x -> Bool.False
4238 | MOVX x -> Bool.False
4239 | SETB x -> Bool.False
4240 | PUSH x -> Bool.False
4241 | POP x -> Bool.False
4242 | XCH (x, x0) -> Bool.False
4243 | XCHD (x, x0) -> Bool.False
4245 | RETI -> Bool.False
4247 | JMP x -> Bool.False)
4250 | ADD (x, x0) -> Bool.False
4251 | ADDC (x, x0) -> Bool.False
4252 | SUBB (x, x0) -> Bool.False
4253 | INC x -> Bool.False
4254 | DEC x -> Bool.False
4255 | MUL (x, x0) -> Bool.False
4256 | DIV (x, x0) -> Bool.False
4257 | DA x -> Bool.False
4258 | JC x -> Bool.False
4259 | JNC x -> Bool.False
4260 | JB (x, x0) -> Bool.False
4261 | JNB (x, x0) -> Bool.False
4262 | JBC (x, x0) -> Bool.False
4263 | JZ x -> Bool.False
4264 | JNZ x -> Bool.False
4265 | CJNE (x, x0) -> Bool.False
4266 | DJNZ (x, x0) -> Bool.False
4267 | ANL x -> Bool.False
4268 | ORL x -> Bool.False
4269 | XRL x -> Bool.False
4270 | CLR x -> Bool.False
4271 | CPL x -> Bool.False
4274 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4275 Vector.VEmpty)) arg)
4276 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4277 Vector.VEmpty)) arg')
4278 | RLC x -> Bool.False
4279 | RR x -> Bool.False
4280 | RRC x -> Bool.False
4281 | SWAP x -> Bool.False
4282 | MOV x -> Bool.False
4283 | MOVX x -> Bool.False
4284 | SETB x -> Bool.False
4285 | PUSH x -> Bool.False
4286 | POP x -> Bool.False
4287 | XCH (x, x0) -> Bool.False
4288 | XCHD (x, x0) -> Bool.False
4290 | RETI -> Bool.False
4292 | JMP x -> Bool.False)
4295 | ADD (x, x0) -> Bool.False
4296 | ADDC (x, x0) -> Bool.False
4297 | SUBB (x, x0) -> Bool.False
4298 | INC x -> Bool.False
4299 | DEC x -> Bool.False
4300 | MUL (x, x0) -> Bool.False
4301 | DIV (x, x0) -> Bool.False
4302 | DA x -> Bool.False
4303 | JC x -> Bool.False
4304 | JNC x -> Bool.False
4305 | JB (x, x0) -> Bool.False
4306 | JNB (x, x0) -> Bool.False
4307 | JBC (x, x0) -> Bool.False
4308 | JZ x -> Bool.False
4309 | JNZ x -> Bool.False
4310 | CJNE (x, x0) -> Bool.False
4311 | DJNZ (x, x0) -> Bool.False
4312 | ANL x -> Bool.False
4313 | ORL x -> Bool.False
4314 | XRL x -> Bool.False
4315 | CLR x -> Bool.False
4316 | CPL x -> Bool.False
4317 | RL x -> Bool.False
4320 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4321 Vector.VEmpty)) arg)
4322 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4323 Vector.VEmpty)) arg')
4324 | RR x -> Bool.False
4325 | RRC x -> Bool.False
4326 | SWAP x -> Bool.False
4327 | MOV x -> Bool.False
4328 | MOVX x -> Bool.False
4329 | SETB x -> Bool.False
4330 | PUSH x -> Bool.False
4331 | POP x -> Bool.False
4332 | XCH (x, x0) -> Bool.False
4333 | XCHD (x, x0) -> Bool.False
4335 | RETI -> Bool.False
4337 | JMP x -> Bool.False)
4340 | ADD (x, x0) -> Bool.False
4341 | ADDC (x, x0) -> Bool.False
4342 | SUBB (x, x0) -> Bool.False
4343 | INC x -> Bool.False
4344 | DEC x -> Bool.False
4345 | MUL (x, x0) -> Bool.False
4346 | DIV (x, x0) -> Bool.False
4347 | DA x -> Bool.False
4348 | JC x -> Bool.False
4349 | JNC x -> Bool.False
4350 | JB (x, x0) -> Bool.False
4351 | JNB (x, x0) -> Bool.False
4352 | JBC (x, x0) -> Bool.False
4353 | JZ x -> Bool.False
4354 | JNZ x -> Bool.False
4355 | CJNE (x, x0) -> Bool.False
4356 | DJNZ (x, x0) -> Bool.False
4357 | ANL x -> Bool.False
4358 | ORL x -> Bool.False
4359 | XRL x -> Bool.False
4360 | CLR x -> Bool.False
4361 | CPL x -> Bool.False
4362 | RL x -> Bool.False
4363 | RLC x -> Bool.False
4366 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4367 Vector.VEmpty)) arg)
4368 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4369 Vector.VEmpty)) arg')
4370 | RRC x -> Bool.False
4371 | SWAP x -> Bool.False
4372 | MOV x -> Bool.False
4373 | MOVX x -> Bool.False
4374 | SETB x -> Bool.False
4375 | PUSH x -> Bool.False
4376 | POP x -> Bool.False
4377 | XCH (x, x0) -> Bool.False
4378 | XCHD (x, x0) -> Bool.False
4380 | RETI -> Bool.False
4382 | JMP x -> Bool.False)
4385 | ADD (x, x0) -> Bool.False
4386 | ADDC (x, x0) -> Bool.False
4387 | SUBB (x, x0) -> Bool.False
4388 | INC x -> Bool.False
4389 | DEC x -> Bool.False
4390 | MUL (x, x0) -> Bool.False
4391 | DIV (x, x0) -> Bool.False
4392 | DA x -> Bool.False
4393 | JC x -> Bool.False
4394 | JNC x -> Bool.False
4395 | JB (x, x0) -> Bool.False
4396 | JNB (x, x0) -> Bool.False
4397 | JBC (x, x0) -> Bool.False
4398 | JZ x -> Bool.False
4399 | JNZ x -> Bool.False
4400 | CJNE (x, x0) -> Bool.False
4401 | DJNZ (x, x0) -> Bool.False
4402 | ANL x -> Bool.False
4403 | ORL x -> Bool.False
4404 | XRL x -> Bool.False
4405 | CLR x -> Bool.False
4406 | CPL x -> Bool.False
4407 | RL x -> Bool.False
4408 | RLC x -> Bool.False
4409 | RR x -> Bool.False
4412 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4413 Vector.VEmpty)) arg)
4414 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4415 Vector.VEmpty)) arg')
4416 | SWAP x -> Bool.False
4417 | MOV x -> Bool.False
4418 | MOVX x -> Bool.False
4419 | SETB x -> Bool.False
4420 | PUSH x -> Bool.False
4421 | POP x -> Bool.False
4422 | XCH (x, x0) -> Bool.False
4423 | XCHD (x, x0) -> Bool.False
4425 | RETI -> Bool.False
4427 | JMP x -> Bool.False)
4430 | ADD (x, x0) -> Bool.False
4431 | ADDC (x, x0) -> Bool.False
4432 | SUBB (x, x0) -> Bool.False
4433 | INC x -> Bool.False
4434 | DEC x -> Bool.False
4435 | MUL (x, x0) -> Bool.False
4436 | DIV (x, x0) -> Bool.False
4437 | DA x -> Bool.False
4438 | JC x -> Bool.False
4439 | JNC x -> Bool.False
4440 | JB (x, x0) -> Bool.False
4441 | JNB (x, x0) -> Bool.False
4442 | JBC (x, x0) -> Bool.False
4443 | JZ x -> Bool.False
4444 | JNZ x -> Bool.False
4445 | CJNE (x, x0) -> Bool.False
4446 | DJNZ (x, x0) -> Bool.False
4447 | ANL x -> Bool.False
4448 | ORL x -> Bool.False
4449 | XRL x -> Bool.False
4450 | CLR x -> Bool.False
4451 | CPL x -> Bool.False
4452 | RL x -> Bool.False
4453 | RLC x -> Bool.False
4454 | RR x -> Bool.False
4455 | RRC x -> Bool.False
4458 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4459 Vector.VEmpty)) arg)
4460 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4461 Vector.VEmpty)) arg')
4462 | MOV x -> Bool.False
4463 | MOVX x -> Bool.False
4464 | SETB x -> Bool.False
4465 | PUSH x -> Bool.False
4466 | POP x -> Bool.False
4467 | XCH (x, x0) -> Bool.False
4468 | XCHD (x, x0) -> Bool.False
4470 | RETI -> Bool.False
4472 | JMP x -> Bool.False)
4475 | ADD (x, x0) -> Bool.False
4476 | ADDC (x, x0) -> Bool.False
4477 | SUBB (x, x0) -> Bool.False
4478 | INC x -> Bool.False
4479 | DEC x -> Bool.False
4480 | MUL (x, x0) -> Bool.False
4481 | DIV (x, x0) -> Bool.False
4482 | DA x -> Bool.False
4483 | JC x -> Bool.False
4484 | JNC x -> Bool.False
4485 | JB (x, x0) -> Bool.False
4486 | JNB (x, x0) -> Bool.False
4487 | JBC (x, x0) -> Bool.False
4488 | JZ x -> Bool.False
4489 | JNZ x -> Bool.False
4490 | CJNE (x, x0) -> Bool.False
4491 | DJNZ (x, x0) -> Bool.False
4492 | ANL x -> Bool.False
4493 | ORL x -> Bool.False
4494 | XRL x -> Bool.False
4495 | CLR x -> Bool.False
4496 | CPL x -> Bool.False
4497 | RL x -> Bool.False
4498 | RLC x -> Bool.False
4499 | RR x -> Bool.False
4500 | RRC x -> Bool.False
4501 | SWAP x -> Bool.False
4504 Util.eq_prod (fun h h1 ->
4506 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4508 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4509 Vector.VEmpty)) h1)) (fun h h1 ->
4511 (subaddressing_modeel (Nat.S (Nat.S (Nat.S Nat.O)))
4512 (Vector.VCons ((Nat.S (Nat.S (Nat.S Nat.O))), Registr,
4513 (Vector.VCons ((Nat.S (Nat.S Nat.O)), Direct, (Vector.VCons
4514 ((Nat.S Nat.O), Indirect, (Vector.VCons (Nat.O, Data,
4515 Vector.VEmpty)))))))) h)
4516 (subaddressing_modeel (Nat.S (Nat.S (Nat.S Nat.O)))
4517 (Vector.VCons ((Nat.S (Nat.S (Nat.S Nat.O))), Registr,
4518 (Vector.VCons ((Nat.S (Nat.S Nat.O)), Direct, (Vector.VCons
4519 ((Nat.S Nat.O), Indirect, (Vector.VCons (Nat.O, Data,
4520 Vector.VEmpty)))))))) h1))
4523 Util.eq_prod (fun h h1 ->
4525 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S
4526 Nat.O), Registr, (Vector.VCons (Nat.O, Indirect,
4527 Vector.VEmpty)))) h)
4528 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S
4529 Nat.O), Registr, (Vector.VCons (Nat.O, Indirect,
4530 Vector.VEmpty)))) h1)) (fun h h1 ->
4532 (subaddressing_modeel (Nat.S (Nat.S Nat.O)) (Vector.VCons
4533 ((Nat.S (Nat.S Nat.O)), Acc_a, (Vector.VCons ((Nat.S Nat.O),
4534 Direct, (Vector.VCons (Nat.O, Data, Vector.VEmpty)))))) h)
4535 (subaddressing_modeel (Nat.S (Nat.S Nat.O)) (Vector.VCons
4536 ((Nat.S (Nat.S Nat.O)), Acc_a, (Vector.VCons ((Nat.S Nat.O),
4537 Direct, (Vector.VCons (Nat.O, Data, Vector.VEmpty)))))) h1))
4540 Util.eq_prod (fun h h1 ->
4542 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Direct,
4544 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Direct,
4545 Vector.VEmpty)) h1)) (fun h h1 ->
4547 (subaddressing_modeel (Nat.S (Nat.S (Nat.S (Nat.S Nat.O))))
4548 (Vector.VCons ((Nat.S (Nat.S (Nat.S (Nat.S Nat.O)))), Acc_a,
4549 (Vector.VCons ((Nat.S (Nat.S (Nat.S Nat.O))), Registr,
4550 (Vector.VCons ((Nat.S (Nat.S Nat.O)), Direct, (Vector.VCons
4551 ((Nat.S Nat.O), Indirect, (Vector.VCons (Nat.O, Data,
4552 Vector.VEmpty)))))))))) h)
4553 (subaddressing_modeel (Nat.S (Nat.S (Nat.S (Nat.S Nat.O))))
4554 (Vector.VCons ((Nat.S (Nat.S (Nat.S (Nat.S Nat.O)))), Acc_a,
4555 (Vector.VCons ((Nat.S (Nat.S (Nat.S Nat.O))), Registr,
4556 (Vector.VCons ((Nat.S (Nat.S Nat.O)), Direct, (Vector.VCons
4557 ((Nat.S Nat.O), Indirect, (Vector.VCons (Nat.O, Data,
4558 Vector.VEmpty)))))))))) h1))
4561 Util.eq_prod (fun h h1 ->
4563 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Dptr,
4565 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Dptr,
4566 Vector.VEmpty)) h1)) (fun h h1 ->
4568 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Data16,
4570 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Data16,
4571 Vector.VEmpty)) h1))
4574 Util.eq_prod (fun h h1 ->
4576 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Carry,
4578 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Carry,
4579 Vector.VEmpty)) h1)) (fun h h1 ->
4581 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Bit_addr,
4583 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Bit_addr,
4584 Vector.VEmpty)) h1))
4587 Util.eq_prod (fun h h1 ->
4589 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Bit_addr,
4591 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Bit_addr,
4592 Vector.VEmpty)) h1)) (fun h h1 ->
4594 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Carry,
4596 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Carry,
4597 Vector.VEmpty)) h1))
4599 let sum_eq_1 = Util.eq_sum prod_eq_6 prod_eq_5 in
4600 let sum_eq_2 = Util.eq_sum sum_eq_1 prod_eq_4 in
4601 let sum_eq_3 = Util.eq_sum sum_eq_2 prod_eq_3 in
4602 let sum_eq_4 = Util.eq_sum sum_eq_3 prod_eq_2 in
4603 let sum_eq_5 = Util.eq_sum sum_eq_4 prod_eq_1 in sum_eq_5 arg arg'
4604 | MOVX x -> Bool.False
4605 | SETB x -> Bool.False
4606 | PUSH x -> Bool.False
4607 | POP x -> Bool.False
4608 | XCH (x, x0) -> Bool.False
4609 | XCHD (x, x0) -> Bool.False
4611 | RETI -> Bool.False
4613 | JMP x -> Bool.False)
4616 | ADD (x, x0) -> Bool.False
4617 | ADDC (x, x0) -> Bool.False
4618 | SUBB (x, x0) -> Bool.False
4619 | INC x -> Bool.False
4620 | DEC x -> Bool.False
4621 | MUL (x, x0) -> Bool.False
4622 | DIV (x, x0) -> Bool.False
4623 | DA x -> Bool.False
4624 | JC x -> Bool.False
4625 | JNC x -> Bool.False
4626 | JB (x, x0) -> Bool.False
4627 | JNB (x, x0) -> Bool.False
4628 | JBC (x, x0) -> Bool.False
4629 | JZ x -> Bool.False
4630 | JNZ x -> Bool.False
4631 | CJNE (x, x0) -> Bool.False
4632 | DJNZ (x, x0) -> Bool.False
4633 | ANL x -> Bool.False
4634 | ORL x -> Bool.False
4635 | XRL x -> Bool.False
4636 | CLR x -> Bool.False
4637 | CPL x -> Bool.False
4638 | RL x -> Bool.False
4639 | RLC x -> Bool.False
4640 | RR x -> Bool.False
4641 | RRC x -> Bool.False
4642 | SWAP x -> Bool.False
4643 | MOV x -> Bool.False
4646 Util.eq_prod (fun h h1 ->
4648 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4650 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4651 Vector.VEmpty)) h1)) (fun h h1 ->
4653 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S
4654 Nat.O), Ext_indirect, (Vector.VCons (Nat.O, Ext_indirect_dptr,
4655 Vector.VEmpty)))) h)
4656 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S
4657 Nat.O), Ext_indirect, (Vector.VCons (Nat.O, Ext_indirect_dptr,
4658 Vector.VEmpty)))) h1))
4661 Util.eq_prod (fun h h1 ->
4663 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S
4664 Nat.O), Ext_indirect, (Vector.VCons (Nat.O, Ext_indirect_dptr,
4665 Vector.VEmpty)))) h)
4666 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S
4667 Nat.O), Ext_indirect, (Vector.VCons (Nat.O, Ext_indirect_dptr,
4668 Vector.VEmpty)))) h1)) (fun h h1 ->
4670 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4672 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4673 Vector.VEmpty)) h1))
4675 let sum_eq = Util.eq_sum prod_eq_left prod_eq_right in sum_eq arg arg'
4676 | SETB x -> Bool.False
4677 | PUSH x -> Bool.False
4678 | POP x -> Bool.False
4679 | XCH (x, x0) -> Bool.False
4680 | XCHD (x, x0) -> Bool.False
4682 | RETI -> Bool.False
4684 | JMP x -> Bool.False)
4687 | ADD (x, x0) -> Bool.False
4688 | ADDC (x, x0) -> Bool.False
4689 | SUBB (x, x0) -> Bool.False
4690 | INC x -> Bool.False
4691 | DEC x -> Bool.False
4692 | MUL (x, x0) -> Bool.False
4693 | DIV (x, x0) -> Bool.False
4694 | DA x -> Bool.False
4695 | JC x -> Bool.False
4696 | JNC x -> Bool.False
4697 | JB (x, x0) -> Bool.False
4698 | JNB (x, x0) -> Bool.False
4699 | JBC (x, x0) -> Bool.False
4700 | JZ x -> Bool.False
4701 | JNZ x -> Bool.False
4702 | CJNE (x, x0) -> Bool.False
4703 | DJNZ (x, x0) -> Bool.False
4704 | ANL x -> Bool.False
4705 | ORL x -> Bool.False
4706 | XRL x -> Bool.False
4707 | CLR x -> Bool.False
4708 | CPL x -> Bool.False
4709 | RL x -> Bool.False
4710 | RLC x -> Bool.False
4711 | RR x -> Bool.False
4712 | RRC x -> Bool.False
4713 | SWAP x -> Bool.False
4714 | MOV x -> Bool.False
4715 | MOVX x -> Bool.False
4718 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S Nat.O),
4719 Carry, (Vector.VCons (Nat.O, Bit_addr, Vector.VEmpty)))) arg)
4720 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S Nat.O),
4721 Carry, (Vector.VCons (Nat.O, Bit_addr, Vector.VEmpty)))) arg')
4722 | PUSH x -> Bool.False
4723 | POP x -> Bool.False
4724 | XCH (x, x0) -> Bool.False
4725 | XCHD (x, x0) -> Bool.False
4727 | RETI -> Bool.False
4729 | JMP x -> Bool.False)
4732 | ADD (x, x0) -> Bool.False
4733 | ADDC (x, x0) -> Bool.False
4734 | SUBB (x, x0) -> Bool.False
4735 | INC x -> Bool.False
4736 | DEC x -> Bool.False
4737 | MUL (x, x0) -> Bool.False
4738 | DIV (x, x0) -> Bool.False
4739 | DA x -> Bool.False
4740 | JC x -> Bool.False
4741 | JNC x -> Bool.False
4742 | JB (x, x0) -> Bool.False
4743 | JNB (x, x0) -> Bool.False
4744 | JBC (x, x0) -> Bool.False
4745 | JZ x -> Bool.False
4746 | JNZ x -> Bool.False
4747 | CJNE (x, x0) -> Bool.False
4748 | DJNZ (x, x0) -> Bool.False
4749 | ANL x -> Bool.False
4750 | ORL x -> Bool.False
4751 | XRL x -> Bool.False
4752 | CLR x -> Bool.False
4753 | CPL x -> Bool.False
4754 | RL x -> Bool.False
4755 | RLC x -> Bool.False
4756 | RR x -> Bool.False
4757 | RRC x -> Bool.False
4758 | SWAP x -> Bool.False
4759 | MOV x -> Bool.False
4760 | MOVX x -> Bool.False
4761 | SETB x -> Bool.False
4764 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Direct,
4765 Vector.VEmpty)) arg)
4766 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Direct,
4767 Vector.VEmpty)) arg')
4768 | POP x -> Bool.False
4769 | XCH (x, x0) -> Bool.False
4770 | XCHD (x, x0) -> Bool.False
4772 | RETI -> Bool.False
4774 | JMP x -> Bool.False)
4777 | ADD (x, x0) -> Bool.False
4778 | ADDC (x, x0) -> Bool.False
4779 | SUBB (x, x0) -> Bool.False
4780 | INC x -> Bool.False
4781 | DEC x -> Bool.False
4782 | MUL (x, x0) -> Bool.False
4783 | DIV (x, x0) -> Bool.False
4784 | DA x -> Bool.False
4785 | JC x -> Bool.False
4786 | JNC x -> Bool.False
4787 | JB (x, x0) -> Bool.False
4788 | JNB (x, x0) -> Bool.False
4789 | JBC (x, x0) -> Bool.False
4790 | JZ x -> Bool.False
4791 | JNZ x -> Bool.False
4792 | CJNE (x, x0) -> Bool.False
4793 | DJNZ (x, x0) -> Bool.False
4794 | ANL x -> Bool.False
4795 | ORL x -> Bool.False
4796 | XRL x -> Bool.False
4797 | CLR x -> Bool.False
4798 | CPL x -> Bool.False
4799 | RL x -> Bool.False
4800 | RLC x -> Bool.False
4801 | RR x -> Bool.False
4802 | RRC x -> Bool.False
4803 | SWAP x -> Bool.False
4804 | MOV x -> Bool.False
4805 | MOVX x -> Bool.False
4806 | SETB x -> Bool.False
4807 | PUSH x -> Bool.False
4810 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Direct,
4811 Vector.VEmpty)) arg)
4812 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Direct,
4813 Vector.VEmpty)) arg')
4814 | XCH (x, x0) -> Bool.False
4815 | XCHD (x, x0) -> Bool.False
4817 | RETI -> Bool.False
4819 | JMP x -> Bool.False)
4820 | XCH (arg1, arg2) ->
4822 | ADD (x, x0) -> Bool.False
4823 | ADDC (x, x0) -> Bool.False
4824 | SUBB (x, x0) -> Bool.False
4825 | INC x -> Bool.False
4826 | DEC x -> Bool.False
4827 | MUL (x, x0) -> Bool.False
4828 | DIV (x, x0) -> Bool.False
4829 | DA x -> Bool.False
4830 | JC x -> Bool.False
4831 | JNC x -> Bool.False
4832 | JB (x, x0) -> Bool.False
4833 | JNB (x, x0) -> Bool.False
4834 | JBC (x, x0) -> Bool.False
4835 | JZ x -> Bool.False
4836 | JNZ x -> Bool.False
4837 | CJNE (x, x0) -> Bool.False
4838 | DJNZ (x, x0) -> Bool.False
4839 | ANL x -> Bool.False
4840 | ORL x -> Bool.False
4841 | XRL x -> Bool.False
4842 | CLR x -> Bool.False
4843 | CPL x -> Bool.False
4844 | RL x -> Bool.False
4845 | RLC x -> Bool.False
4846 | RR x -> Bool.False
4847 | RRC x -> Bool.False
4848 | SWAP x -> Bool.False
4849 | MOV x -> Bool.False
4850 | MOVX x -> Bool.False
4851 | SETB x -> Bool.False
4852 | PUSH x -> Bool.False
4853 | POP x -> Bool.False
4854 | XCH (arg1', arg2') ->
4857 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4858 Vector.VEmpty)) arg1)
4859 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4860 Vector.VEmpty)) arg1'))
4862 (subaddressing_modeel (Nat.S (Nat.S Nat.O)) (Vector.VCons ((Nat.S
4863 (Nat.S Nat.O)), Registr, (Vector.VCons ((Nat.S Nat.O), Direct,
4864 (Vector.VCons (Nat.O, Indirect, Vector.VEmpty)))))) arg2)
4865 (subaddressing_modeel (Nat.S (Nat.S Nat.O)) (Vector.VCons ((Nat.S
4866 (Nat.S Nat.O)), Registr, (Vector.VCons ((Nat.S Nat.O), Direct,
4867 (Vector.VCons (Nat.O, Indirect, Vector.VEmpty)))))) arg2'))
4868 | XCHD (x, x0) -> Bool.False
4870 | RETI -> Bool.False
4872 | JMP x -> Bool.False)
4873 | XCHD (arg1, arg2) ->
4875 | ADD (x, x0) -> Bool.False
4876 | ADDC (x, x0) -> Bool.False
4877 | SUBB (x, x0) -> Bool.False
4878 | INC x -> Bool.False
4879 | DEC x -> Bool.False
4880 | MUL (x, x0) -> Bool.False
4881 | DIV (x, x0) -> Bool.False
4882 | DA x -> Bool.False
4883 | JC x -> Bool.False
4884 | JNC x -> Bool.False
4885 | JB (x, x0) -> Bool.False
4886 | JNB (x, x0) -> Bool.False
4887 | JBC (x, x0) -> Bool.False
4888 | JZ x -> Bool.False
4889 | JNZ x -> Bool.False
4890 | CJNE (x, x0) -> Bool.False
4891 | DJNZ (x, x0) -> Bool.False
4892 | ANL x -> Bool.False
4893 | ORL x -> Bool.False
4894 | XRL x -> Bool.False
4895 | CLR x -> Bool.False
4896 | CPL x -> Bool.False
4897 | RL x -> Bool.False
4898 | RLC x -> Bool.False
4899 | RR x -> Bool.False
4900 | RRC x -> Bool.False
4901 | SWAP x -> Bool.False
4902 | MOV x -> Bool.False
4903 | MOVX x -> Bool.False
4904 | SETB x -> Bool.False
4905 | PUSH x -> Bool.False
4906 | POP x -> Bool.False
4907 | XCH (x, x0) -> Bool.False
4908 | XCHD (arg1', arg2') ->
4911 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4912 Vector.VEmpty)) arg1)
4913 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
4914 Vector.VEmpty)) arg1'))
4916 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Indirect,
4917 Vector.VEmpty)) arg2)
4918 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Indirect,
4919 Vector.VEmpty)) arg2'))
4921 | RETI -> Bool.False
4923 | JMP x -> Bool.False)
4926 | ADD (x, x0) -> Bool.False
4927 | ADDC (x, x0) -> Bool.False
4928 | SUBB (x, x0) -> Bool.False
4929 | INC x -> Bool.False
4930 | DEC x -> Bool.False
4931 | MUL (x, x0) -> Bool.False
4932 | DIV (x, x0) -> Bool.False
4933 | DA x -> Bool.False
4934 | JC x -> Bool.False
4935 | JNC x -> Bool.False
4936 | JB (x, x0) -> Bool.False
4937 | JNB (x, x0) -> Bool.False
4938 | JBC (x, x0) -> Bool.False
4939 | JZ x -> Bool.False
4940 | JNZ x -> Bool.False
4941 | CJNE (x, x0) -> Bool.False
4942 | DJNZ (x, x0) -> Bool.False
4943 | ANL x -> Bool.False
4944 | ORL x -> Bool.False
4945 | XRL x -> Bool.False
4946 | CLR x -> Bool.False
4947 | CPL x -> Bool.False
4948 | RL x -> Bool.False
4949 | RLC x -> Bool.False
4950 | RR x -> Bool.False
4951 | RRC x -> Bool.False
4952 | SWAP x -> Bool.False
4953 | MOV x -> Bool.False
4954 | MOVX x -> Bool.False
4955 | SETB x -> Bool.False
4956 | PUSH x -> Bool.False
4957 | POP x -> Bool.False
4958 | XCH (x, x0) -> Bool.False
4959 | XCHD (x, x0) -> Bool.False
4961 | RETI -> Bool.False
4963 | JMP x -> Bool.False)
4966 | ADD (x, x0) -> Bool.False
4967 | ADDC (x, x0) -> Bool.False
4968 | SUBB (x, x0) -> Bool.False
4969 | INC x -> Bool.False
4970 | DEC x -> Bool.False
4971 | MUL (x, x0) -> Bool.False
4972 | DIV (x, x0) -> Bool.False
4973 | DA x -> Bool.False
4974 | JC x -> Bool.False
4975 | JNC x -> Bool.False
4976 | JB (x, x0) -> Bool.False
4977 | JNB (x, x0) -> Bool.False
4978 | JBC (x, x0) -> Bool.False
4979 | JZ x -> Bool.False
4980 | JNZ x -> Bool.False
4981 | CJNE (x, x0) -> Bool.False
4982 | DJNZ (x, x0) -> Bool.False
4983 | ANL x -> Bool.False
4984 | ORL x -> Bool.False
4985 | XRL x -> Bool.False
4986 | CLR x -> Bool.False
4987 | CPL x -> Bool.False
4988 | RL x -> Bool.False
4989 | RLC x -> Bool.False
4990 | RR x -> Bool.False
4991 | RRC x -> Bool.False
4992 | SWAP x -> Bool.False
4993 | MOV x -> Bool.False
4994 | MOVX x -> Bool.False
4995 | SETB x -> Bool.False
4996 | PUSH x -> Bool.False
4997 | POP x -> Bool.False
4998 | XCH (x, x0) -> Bool.False
4999 | XCHD (x, x0) -> Bool.False
5003 | JMP x -> Bool.False)
5006 | ADD (x, x0) -> Bool.False
5007 | ADDC (x, x0) -> Bool.False
5008 | SUBB (x, x0) -> Bool.False
5009 | INC x -> Bool.False
5010 | DEC x -> Bool.False
5011 | MUL (x, x0) -> Bool.False
5012 | DIV (x, x0) -> Bool.False
5013 | DA x -> Bool.False
5014 | JC x -> Bool.False
5015 | JNC x -> Bool.False
5016 | JB (x, x0) -> Bool.False
5017 | JNB (x, x0) -> Bool.False
5018 | JBC (x, x0) -> Bool.False
5019 | JZ x -> Bool.False
5020 | JNZ x -> Bool.False
5021 | CJNE (x, x0) -> Bool.False
5022 | DJNZ (x, x0) -> Bool.False
5023 | ANL x -> Bool.False
5024 | ORL x -> Bool.False
5025 | XRL x -> Bool.False
5026 | CLR x -> Bool.False
5027 | CPL x -> Bool.False
5028 | RL x -> Bool.False
5029 | RLC x -> Bool.False
5030 | RR x -> Bool.False
5031 | RRC x -> Bool.False
5032 | SWAP x -> Bool.False
5033 | MOV x -> Bool.False
5034 | MOVX x -> Bool.False
5035 | SETB x -> Bool.False
5036 | PUSH x -> Bool.False
5037 | POP x -> Bool.False
5038 | XCH (x, x0) -> Bool.False
5039 | XCHD (x, x0) -> Bool.False
5041 | RETI -> Bool.False
5043 | JMP x -> Bool.False)
5046 | ADD (x, x0) -> Bool.False
5047 | ADDC (x, x0) -> Bool.False
5048 | SUBB (x, x0) -> Bool.False
5049 | INC x -> Bool.False
5050 | DEC x -> Bool.False
5051 | MUL (x, x0) -> Bool.False
5052 | DIV (x, x0) -> Bool.False
5053 | DA x -> Bool.False
5054 | JC x -> Bool.False
5055 | JNC x -> Bool.False
5056 | JB (x, x0) -> Bool.False
5057 | JNB (x, x0) -> Bool.False
5058 | JBC (x, x0) -> Bool.False
5059 | JZ x -> Bool.False
5060 | JNZ x -> Bool.False
5061 | CJNE (x, x0) -> Bool.False
5062 | DJNZ (x, x0) -> Bool.False
5063 | ANL x -> Bool.False
5064 | ORL x -> Bool.False
5065 | XRL x -> Bool.False
5066 | CLR x -> Bool.False
5067 | CPL x -> Bool.False
5068 | RL x -> Bool.False
5069 | RLC x -> Bool.False
5070 | RR x -> Bool.False
5071 | RRC x -> Bool.False
5072 | SWAP x -> Bool.False
5073 | MOV x -> Bool.False
5074 | MOVX x -> Bool.False
5075 | SETB x -> Bool.False
5076 | PUSH x -> Bool.False
5077 | POP x -> Bool.False
5078 | XCH (x, x0) -> Bool.False
5079 | XCHD (x, x0) -> Bool.False
5081 | RETI -> Bool.False
5085 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_dptr,
5086 Vector.VEmpty)) arg)
5087 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_dptr,
5088 Vector.VEmpty)) arg'))
5091 | ACALL of subaddressing_mode
5092 | LCALL of subaddressing_mode
5093 | AJMP of subaddressing_mode
5094 | LJMP of subaddressing_mode
5095 | SJMP of subaddressing_mode
5096 | MOVC of subaddressing_mode * subaddressing_mode
5097 | RealInstruction of subaddressing_mode preinstruction
5099 (** val instruction_rect_Type4 :
5100 (subaddressing_mode -> 'a1) -> (subaddressing_mode -> 'a1) ->
5101 (subaddressing_mode -> 'a1) -> (subaddressing_mode -> 'a1) ->
5102 (subaddressing_mode -> 'a1) -> (subaddressing_mode -> subaddressing_mode
5103 -> 'a1) -> (subaddressing_mode preinstruction -> 'a1) -> instruction ->
5105 let rec instruction_rect_Type4 h_ACALL h_LCALL h_AJMP h_LJMP h_SJMP h_MOVC h_RealInstruction = function
5106 | ACALL x_1825 -> h_ACALL x_1825
5107 | LCALL x_1826 -> h_LCALL x_1826
5108 | AJMP x_1827 -> h_AJMP x_1827
5109 | LJMP x_1828 -> h_LJMP x_1828
5110 | SJMP x_1829 -> h_SJMP x_1829
5111 | MOVC (x_1831, x_1830) -> h_MOVC x_1831 x_1830
5112 | RealInstruction x_1832 -> h_RealInstruction x_1832
5114 (** val instruction_rect_Type5 :
5115 (subaddressing_mode -> 'a1) -> (subaddressing_mode -> 'a1) ->
5116 (subaddressing_mode -> 'a1) -> (subaddressing_mode -> 'a1) ->
5117 (subaddressing_mode -> 'a1) -> (subaddressing_mode -> subaddressing_mode
5118 -> 'a1) -> (subaddressing_mode preinstruction -> 'a1) -> instruction ->
5120 let rec instruction_rect_Type5 h_ACALL h_LCALL h_AJMP h_LJMP h_SJMP h_MOVC h_RealInstruction = function
5121 | ACALL x_1841 -> h_ACALL x_1841
5122 | LCALL x_1842 -> h_LCALL x_1842
5123 | AJMP x_1843 -> h_AJMP x_1843
5124 | LJMP x_1844 -> h_LJMP x_1844
5125 | SJMP x_1845 -> h_SJMP x_1845
5126 | MOVC (x_1847, x_1846) -> h_MOVC x_1847 x_1846
5127 | RealInstruction x_1848 -> h_RealInstruction x_1848
5129 (** val instruction_rect_Type3 :
5130 (subaddressing_mode -> 'a1) -> (subaddressing_mode -> 'a1) ->
5131 (subaddressing_mode -> 'a1) -> (subaddressing_mode -> 'a1) ->
5132 (subaddressing_mode -> 'a1) -> (subaddressing_mode -> subaddressing_mode
5133 -> 'a1) -> (subaddressing_mode preinstruction -> 'a1) -> instruction ->
5135 let rec instruction_rect_Type3 h_ACALL h_LCALL h_AJMP h_LJMP h_SJMP h_MOVC h_RealInstruction = function
5136 | ACALL x_1857 -> h_ACALL x_1857
5137 | LCALL x_1858 -> h_LCALL x_1858
5138 | AJMP x_1859 -> h_AJMP x_1859
5139 | LJMP x_1860 -> h_LJMP x_1860
5140 | SJMP x_1861 -> h_SJMP x_1861
5141 | MOVC (x_1863, x_1862) -> h_MOVC x_1863 x_1862
5142 | RealInstruction x_1864 -> h_RealInstruction x_1864
5144 (** val instruction_rect_Type2 :
5145 (subaddressing_mode -> 'a1) -> (subaddressing_mode -> 'a1) ->
5146 (subaddressing_mode -> 'a1) -> (subaddressing_mode -> 'a1) ->
5147 (subaddressing_mode -> 'a1) -> (subaddressing_mode -> subaddressing_mode
5148 -> 'a1) -> (subaddressing_mode preinstruction -> 'a1) -> instruction ->
5150 let rec instruction_rect_Type2 h_ACALL h_LCALL h_AJMP h_LJMP h_SJMP h_MOVC h_RealInstruction = function
5151 | ACALL x_1873 -> h_ACALL x_1873
5152 | LCALL x_1874 -> h_LCALL x_1874
5153 | AJMP x_1875 -> h_AJMP x_1875
5154 | LJMP x_1876 -> h_LJMP x_1876
5155 | SJMP x_1877 -> h_SJMP x_1877
5156 | MOVC (x_1879, x_1878) -> h_MOVC x_1879 x_1878
5157 | RealInstruction x_1880 -> h_RealInstruction x_1880
5159 (** val instruction_rect_Type1 :
5160 (subaddressing_mode -> 'a1) -> (subaddressing_mode -> 'a1) ->
5161 (subaddressing_mode -> 'a1) -> (subaddressing_mode -> 'a1) ->
5162 (subaddressing_mode -> 'a1) -> (subaddressing_mode -> subaddressing_mode
5163 -> 'a1) -> (subaddressing_mode preinstruction -> 'a1) -> instruction ->
5165 let rec instruction_rect_Type1 h_ACALL h_LCALL h_AJMP h_LJMP h_SJMP h_MOVC h_RealInstruction = function
5166 | ACALL x_1889 -> h_ACALL x_1889
5167 | LCALL x_1890 -> h_LCALL x_1890
5168 | AJMP x_1891 -> h_AJMP x_1891
5169 | LJMP x_1892 -> h_LJMP x_1892
5170 | SJMP x_1893 -> h_SJMP x_1893
5171 | MOVC (x_1895, x_1894) -> h_MOVC x_1895 x_1894
5172 | RealInstruction x_1896 -> h_RealInstruction x_1896
5174 (** val instruction_rect_Type0 :
5175 (subaddressing_mode -> 'a1) -> (subaddressing_mode -> 'a1) ->
5176 (subaddressing_mode -> 'a1) -> (subaddressing_mode -> 'a1) ->
5177 (subaddressing_mode -> 'a1) -> (subaddressing_mode -> subaddressing_mode
5178 -> 'a1) -> (subaddressing_mode preinstruction -> 'a1) -> instruction ->
5180 let rec instruction_rect_Type0 h_ACALL h_LCALL h_AJMP h_LJMP h_SJMP h_MOVC h_RealInstruction = function
5181 | ACALL x_1905 -> h_ACALL x_1905
5182 | LCALL x_1906 -> h_LCALL x_1906
5183 | AJMP x_1907 -> h_AJMP x_1907
5184 | LJMP x_1908 -> h_LJMP x_1908
5185 | SJMP x_1909 -> h_SJMP x_1909
5186 | MOVC (x_1911, x_1910) -> h_MOVC x_1911 x_1910
5187 | RealInstruction x_1912 -> h_RealInstruction x_1912
5189 (** val instruction_inv_rect_Type4 :
5190 instruction -> (subaddressing_mode -> __ -> 'a1) -> (subaddressing_mode
5191 -> __ -> 'a1) -> (subaddressing_mode -> __ -> 'a1) -> (subaddressing_mode
5192 -> __ -> 'a1) -> (subaddressing_mode -> __ -> 'a1) -> (subaddressing_mode
5193 -> subaddressing_mode -> __ -> 'a1) -> (subaddressing_mode preinstruction
5194 -> __ -> 'a1) -> 'a1 **)
5195 let instruction_inv_rect_Type4 hterm h1 h2 h3 h4 h5 h6 h7 =
5196 let hcut = instruction_rect_Type4 h1 h2 h3 h4 h5 h6 h7 hterm in hcut __
5198 (** val instruction_inv_rect_Type3 :
5199 instruction -> (subaddressing_mode -> __ -> 'a1) -> (subaddressing_mode
5200 -> __ -> 'a1) -> (subaddressing_mode -> __ -> 'a1) -> (subaddressing_mode
5201 -> __ -> 'a1) -> (subaddressing_mode -> __ -> 'a1) -> (subaddressing_mode
5202 -> subaddressing_mode -> __ -> 'a1) -> (subaddressing_mode preinstruction
5203 -> __ -> 'a1) -> 'a1 **)
5204 let instruction_inv_rect_Type3 hterm h1 h2 h3 h4 h5 h6 h7 =
5205 let hcut = instruction_rect_Type3 h1 h2 h3 h4 h5 h6 h7 hterm in hcut __
5207 (** val instruction_inv_rect_Type2 :
5208 instruction -> (subaddressing_mode -> __ -> 'a1) -> (subaddressing_mode
5209 -> __ -> 'a1) -> (subaddressing_mode -> __ -> 'a1) -> (subaddressing_mode
5210 -> __ -> 'a1) -> (subaddressing_mode -> __ -> 'a1) -> (subaddressing_mode
5211 -> subaddressing_mode -> __ -> 'a1) -> (subaddressing_mode preinstruction
5212 -> __ -> 'a1) -> 'a1 **)
5213 let instruction_inv_rect_Type2 hterm h1 h2 h3 h4 h5 h6 h7 =
5214 let hcut = instruction_rect_Type2 h1 h2 h3 h4 h5 h6 h7 hterm in hcut __
5216 (** val instruction_inv_rect_Type1 :
5217 instruction -> (subaddressing_mode -> __ -> 'a1) -> (subaddressing_mode
5218 -> __ -> 'a1) -> (subaddressing_mode -> __ -> 'a1) -> (subaddressing_mode
5219 -> __ -> 'a1) -> (subaddressing_mode -> __ -> 'a1) -> (subaddressing_mode
5220 -> subaddressing_mode -> __ -> 'a1) -> (subaddressing_mode preinstruction
5221 -> __ -> 'a1) -> 'a1 **)
5222 let instruction_inv_rect_Type1 hterm h1 h2 h3 h4 h5 h6 h7 =
5223 let hcut = instruction_rect_Type1 h1 h2 h3 h4 h5 h6 h7 hterm in hcut __
5225 (** val instruction_inv_rect_Type0 :
5226 instruction -> (subaddressing_mode -> __ -> 'a1) -> (subaddressing_mode
5227 -> __ -> 'a1) -> (subaddressing_mode -> __ -> 'a1) -> (subaddressing_mode
5228 -> __ -> 'a1) -> (subaddressing_mode -> __ -> 'a1) -> (subaddressing_mode
5229 -> subaddressing_mode -> __ -> 'a1) -> (subaddressing_mode preinstruction
5230 -> __ -> 'a1) -> 'a1 **)
5231 let instruction_inv_rect_Type0 hterm h1 h2 h3 h4 h5 h6 h7 =
5232 let hcut = instruction_rect_Type0 h1 h2 h3 h4 h5 h6 h7 hterm in hcut __
5234 (** val instruction_discr : instruction -> instruction -> __ **)
5235 let instruction_discr x y =
5236 Logic.eq_rect_Type2 x
5238 | ACALL a0 -> Obj.magic (fun _ dH -> dH __)
5239 | LCALL a0 -> Obj.magic (fun _ dH -> dH __)
5240 | AJMP a0 -> Obj.magic (fun _ dH -> dH __)
5241 | LJMP a0 -> Obj.magic (fun _ dH -> dH __)
5242 | SJMP a0 -> Obj.magic (fun _ dH -> dH __)
5243 | MOVC (a0, a1) -> Obj.magic (fun _ dH -> dH __ __)
5244 | RealInstruction a0 -> Obj.magic (fun _ dH -> dH __)) y
5246 (** val instruction_jmdiscr : instruction -> instruction -> __ **)
5247 let instruction_jmdiscr x y =
5248 Logic.eq_rect_Type2 x
5250 | ACALL a0 -> Obj.magic (fun _ dH -> dH __)
5251 | LCALL a0 -> Obj.magic (fun _ dH -> dH __)
5252 | AJMP a0 -> Obj.magic (fun _ dH -> dH __)
5253 | LJMP a0 -> Obj.magic (fun _ dH -> dH __)
5254 | SJMP a0 -> Obj.magic (fun _ dH -> dH __)
5255 | MOVC (a0, a1) -> Obj.magic (fun _ dH -> dH __ __)
5256 | RealInstruction a0 -> Obj.magic (fun _ dH -> dH __)) y
5258 (** val dpi1__o__RealInstruction__o__inject :
5259 (subaddressing_mode preinstruction, 'a1) Types.dPair -> instruction
5261 let dpi1__o__RealInstruction__o__inject x2 =
5262 RealInstruction x2.Types.dpi1
5264 (** val eject__o__RealInstruction__o__inject :
5265 subaddressing_mode preinstruction Types.sig0 -> instruction Types.sig0 **)
5266 let eject__o__RealInstruction__o__inject x2 =
5267 RealInstruction (Types.pi1 x2)
5269 (** val realInstruction__o__inject :
5270 subaddressing_mode preinstruction -> instruction Types.sig0 **)
5271 let realInstruction__o__inject x1 =
5274 (** val dpi1__o__RealInstruction :
5275 (subaddressing_mode preinstruction, 'a1) Types.dPair -> instruction **)
5276 let dpi1__o__RealInstruction x1 =
5277 RealInstruction x1.Types.dpi1
5279 (** val eject__o__RealInstruction :
5280 subaddressing_mode preinstruction Types.sig0 -> instruction **)
5281 let eject__o__RealInstruction x1 =
5282 RealInstruction (Types.pi1 x1)
5284 (** val eq_instruction : instruction -> instruction -> Bool.bool **)
5285 let eq_instruction i j =
5291 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Addr11,
5292 Vector.VEmpty)) arg)
5293 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Addr11,
5294 Vector.VEmpty)) arg')
5295 | LCALL x -> Bool.False
5296 | AJMP x -> Bool.False
5297 | LJMP x -> Bool.False
5298 | SJMP x -> Bool.False
5299 | MOVC (x, x0) -> Bool.False
5300 | RealInstruction x -> Bool.False)
5303 | ACALL x -> Bool.False
5306 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Addr16,
5307 Vector.VEmpty)) arg)
5308 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Addr16,
5309 Vector.VEmpty)) arg')
5310 | AJMP x -> Bool.False
5311 | LJMP x -> Bool.False
5312 | SJMP x -> Bool.False
5313 | MOVC (x, x0) -> Bool.False
5314 | RealInstruction x -> Bool.False)
5317 | ACALL x -> Bool.False
5318 | LCALL x -> Bool.False
5321 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Addr11,
5322 Vector.VEmpty)) arg)
5323 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Addr11,
5324 Vector.VEmpty)) arg')
5325 | LJMP x -> Bool.False
5326 | SJMP x -> Bool.False
5327 | MOVC (x, x0) -> Bool.False
5328 | RealInstruction x -> Bool.False)
5331 | ACALL x -> Bool.False
5332 | LCALL x -> Bool.False
5333 | AJMP x -> Bool.False
5336 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Addr16,
5337 Vector.VEmpty)) arg)
5338 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Addr16,
5339 Vector.VEmpty)) arg')
5340 | SJMP x -> Bool.False
5341 | MOVC (x, x0) -> Bool.False
5342 | RealInstruction x -> Bool.False)
5345 | ACALL x -> Bool.False
5346 | LCALL x -> Bool.False
5347 | AJMP x -> Bool.False
5348 | LJMP x -> Bool.False
5351 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Relative,
5352 Vector.VEmpty)) arg)
5353 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Relative,
5354 Vector.VEmpty)) arg')
5355 | MOVC (x, x0) -> Bool.False
5356 | RealInstruction x -> Bool.False)
5357 | MOVC (arg1, arg2) ->
5359 | ACALL x -> Bool.False
5360 | LCALL x -> Bool.False
5361 | AJMP x -> Bool.False
5362 | LJMP x -> Bool.False
5363 | SJMP x -> Bool.False
5364 | MOVC (arg1', arg2') ->
5367 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
5368 Vector.VEmpty)) arg1)
5369 (subaddressing_modeel Nat.O (Vector.VCons (Nat.O, Acc_a,
5370 Vector.VEmpty)) arg1'))
5372 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S Nat.O),
5373 Acc_dptr, (Vector.VCons (Nat.O, Acc_pc, Vector.VEmpty)))) arg2)
5374 (subaddressing_modeel (Nat.S Nat.O) (Vector.VCons ((Nat.S Nat.O),
5375 Acc_dptr, (Vector.VCons (Nat.O, Acc_pc, Vector.VEmpty)))) arg2'))
5376 | RealInstruction x -> Bool.False)
5377 | RealInstruction instr ->
5379 | ACALL x -> Bool.False
5380 | LCALL x -> Bool.False
5381 | AJMP x -> Bool.False
5382 | LJMP x -> Bool.False
5383 | SJMP x -> Bool.False
5384 | MOVC (x, x0) -> Bool.False
5385 | RealInstruction instr' -> eq_preinstruction instr instr')
5391 (** val word_side_rect_Type4 : 'a1 -> 'a1 -> word_side -> 'a1 **)
5392 let rec word_side_rect_Type4 h_HIGH h_LOW = function
5396 (** val word_side_rect_Type5 : 'a1 -> 'a1 -> word_side -> 'a1 **)
5397 let rec word_side_rect_Type5 h_HIGH h_LOW = function
5401 (** val word_side_rect_Type3 : 'a1 -> 'a1 -> word_side -> 'a1 **)
5402 let rec word_side_rect_Type3 h_HIGH h_LOW = function
5406 (** val word_side_rect_Type2 : 'a1 -> 'a1 -> word_side -> 'a1 **)
5407 let rec word_side_rect_Type2 h_HIGH h_LOW = function
5411 (** val word_side_rect_Type1 : 'a1 -> 'a1 -> word_side -> 'a1 **)
5412 let rec word_side_rect_Type1 h_HIGH h_LOW = function
5416 (** val word_side_rect_Type0 : 'a1 -> 'a1 -> word_side -> 'a1 **)
5417 let rec word_side_rect_Type0 h_HIGH h_LOW = function
5421 (** val word_side_inv_rect_Type4 :
5422 word_side -> (__ -> 'a1) -> (__ -> 'a1) -> 'a1 **)
5423 let word_side_inv_rect_Type4 hterm h1 h2 =
5424 let hcut = word_side_rect_Type4 h1 h2 hterm in hcut __
5426 (** val word_side_inv_rect_Type3 :
5427 word_side -> (__ -> 'a1) -> (__ -> 'a1) -> 'a1 **)
5428 let word_side_inv_rect_Type3 hterm h1 h2 =
5429 let hcut = word_side_rect_Type3 h1 h2 hterm in hcut __
5431 (** val word_side_inv_rect_Type2 :
5432 word_side -> (__ -> 'a1) -> (__ -> 'a1) -> 'a1 **)
5433 let word_side_inv_rect_Type2 hterm h1 h2 =
5434 let hcut = word_side_rect_Type2 h1 h2 hterm in hcut __
5436 (** val word_side_inv_rect_Type1 :
5437 word_side -> (__ -> 'a1) -> (__ -> 'a1) -> 'a1 **)
5438 let word_side_inv_rect_Type1 hterm h1 h2 =
5439 let hcut = word_side_rect_Type1 h1 h2 hterm in hcut __
5441 (** val word_side_inv_rect_Type0 :
5442 word_side -> (__ -> 'a1) -> (__ -> 'a1) -> 'a1 **)
5443 let word_side_inv_rect_Type0 hterm h1 h2 =
5444 let hcut = word_side_rect_Type0 h1 h2 hterm in hcut __
5446 (** val word_side_discr : word_side -> word_side -> __ **)
5447 let word_side_discr x y =
5448 Logic.eq_rect_Type2 x
5450 | HIGH -> Obj.magic (fun _ dH -> dH)
5451 | LOW -> Obj.magic (fun _ dH -> dH)) y
5453 (** val word_side_jmdiscr : word_side -> word_side -> __ **)
5454 let word_side_jmdiscr x y =
5455 Logic.eq_rect_Type2 x
5457 | HIGH -> Obj.magic (fun _ dH -> dH)
5458 | LOW -> Obj.magic (fun _ dH -> dH)) y
5460 type pseudo_instruction =
5461 | Instruction of identifier preinstruction
5462 | Comment of String.string
5463 | Cost of CostLabel.costlabel
5465 | Jnz of subaddressing_mode * identifier * identifier
5466 | Call of identifier
5467 | Mov of (subaddressing_mode, (subaddressing_mode, word_side) Types.prod)
5468 Types.sum * identifier * BitVector.word
5470 (** val pseudo_instruction_rect_Type4 :
5471 (identifier preinstruction -> 'a1) -> (String.string -> 'a1) ->
5472 (CostLabel.costlabel -> 'a1) -> (identifier -> 'a1) ->
5473 (subaddressing_mode -> identifier -> identifier -> 'a1) -> (identifier ->
5474 'a1) -> ((subaddressing_mode, (subaddressing_mode, word_side) Types.prod)
5475 Types.sum -> identifier -> BitVector.word -> 'a1) -> pseudo_instruction
5477 let rec pseudo_instruction_rect_Type4 h_Instruction h_Comment h_Cost h_Jmp h_Jnz h_Call h_Mov = function
5478 | Instruction x_2075 -> h_Instruction x_2075
5479 | Comment x_2076 -> h_Comment x_2076
5480 | Cost x_2077 -> h_Cost x_2077
5481 | Jmp x_2078 -> h_Jmp x_2078
5482 | Jnz (x_2081, x_2080, x_2079) -> h_Jnz x_2081 x_2080 x_2079
5483 | Call x_2082 -> h_Call x_2082
5484 | Mov (x_2085, x_2084, x_2083) -> h_Mov x_2085 x_2084 x_2083
5486 (** val pseudo_instruction_rect_Type5 :
5487 (identifier preinstruction -> 'a1) -> (String.string -> 'a1) ->
5488 (CostLabel.costlabel -> 'a1) -> (identifier -> 'a1) ->
5489 (subaddressing_mode -> identifier -> identifier -> 'a1) -> (identifier ->
5490 'a1) -> ((subaddressing_mode, (subaddressing_mode, word_side) Types.prod)
5491 Types.sum -> identifier -> BitVector.word -> 'a1) -> pseudo_instruction
5493 let rec pseudo_instruction_rect_Type5 h_Instruction h_Comment h_Cost h_Jmp h_Jnz h_Call h_Mov = function
5494 | Instruction x_2094 -> h_Instruction x_2094
5495 | Comment x_2095 -> h_Comment x_2095
5496 | Cost x_2096 -> h_Cost x_2096
5497 | Jmp x_2097 -> h_Jmp x_2097
5498 | Jnz (x_2100, x_2099, x_2098) -> h_Jnz x_2100 x_2099 x_2098
5499 | Call x_2101 -> h_Call x_2101
5500 | Mov (x_2104, x_2103, x_2102) -> h_Mov x_2104 x_2103 x_2102
5502 (** val pseudo_instruction_rect_Type3 :
5503 (identifier preinstruction -> 'a1) -> (String.string -> 'a1) ->
5504 (CostLabel.costlabel -> 'a1) -> (identifier -> 'a1) ->
5505 (subaddressing_mode -> identifier -> identifier -> 'a1) -> (identifier ->
5506 'a1) -> ((subaddressing_mode, (subaddressing_mode, word_side) Types.prod)
5507 Types.sum -> identifier -> BitVector.word -> 'a1) -> pseudo_instruction
5509 let rec pseudo_instruction_rect_Type3 h_Instruction h_Comment h_Cost h_Jmp h_Jnz h_Call h_Mov = function
5510 | Instruction x_2113 -> h_Instruction x_2113
5511 | Comment x_2114 -> h_Comment x_2114
5512 | Cost x_2115 -> h_Cost x_2115
5513 | Jmp x_2116 -> h_Jmp x_2116
5514 | Jnz (x_2119, x_2118, x_2117) -> h_Jnz x_2119 x_2118 x_2117
5515 | Call x_2120 -> h_Call x_2120
5516 | Mov (x_2123, x_2122, x_2121) -> h_Mov x_2123 x_2122 x_2121
5518 (** val pseudo_instruction_rect_Type2 :
5519 (identifier preinstruction -> 'a1) -> (String.string -> 'a1) ->
5520 (CostLabel.costlabel -> 'a1) -> (identifier -> 'a1) ->
5521 (subaddressing_mode -> identifier -> identifier -> 'a1) -> (identifier ->
5522 'a1) -> ((subaddressing_mode, (subaddressing_mode, word_side) Types.prod)
5523 Types.sum -> identifier -> BitVector.word -> 'a1) -> pseudo_instruction
5525 let rec pseudo_instruction_rect_Type2 h_Instruction h_Comment h_Cost h_Jmp h_Jnz h_Call h_Mov = function
5526 | Instruction x_2132 -> h_Instruction x_2132
5527 | Comment x_2133 -> h_Comment x_2133
5528 | Cost x_2134 -> h_Cost x_2134
5529 | Jmp x_2135 -> h_Jmp x_2135
5530 | Jnz (x_2138, x_2137, x_2136) -> h_Jnz x_2138 x_2137 x_2136
5531 | Call x_2139 -> h_Call x_2139
5532 | Mov (x_2142, x_2141, x_2140) -> h_Mov x_2142 x_2141 x_2140
5534 (** val pseudo_instruction_rect_Type1 :
5535 (identifier preinstruction -> 'a1) -> (String.string -> 'a1) ->
5536 (CostLabel.costlabel -> 'a1) -> (identifier -> 'a1) ->
5537 (subaddressing_mode -> identifier -> identifier -> 'a1) -> (identifier ->
5538 'a1) -> ((subaddressing_mode, (subaddressing_mode, word_side) Types.prod)
5539 Types.sum -> identifier -> BitVector.word -> 'a1) -> pseudo_instruction
5541 let rec pseudo_instruction_rect_Type1 h_Instruction h_Comment h_Cost h_Jmp h_Jnz h_Call h_Mov = function
5542 | Instruction x_2151 -> h_Instruction x_2151
5543 | Comment x_2152 -> h_Comment x_2152
5544 | Cost x_2153 -> h_Cost x_2153
5545 | Jmp x_2154 -> h_Jmp x_2154
5546 | Jnz (x_2157, x_2156, x_2155) -> h_Jnz x_2157 x_2156 x_2155
5547 | Call x_2158 -> h_Call x_2158
5548 | Mov (x_2161, x_2160, x_2159) -> h_Mov x_2161 x_2160 x_2159
5550 (** val pseudo_instruction_rect_Type0 :
5551 (identifier preinstruction -> 'a1) -> (String.string -> 'a1) ->
5552 (CostLabel.costlabel -> 'a1) -> (identifier -> 'a1) ->
5553 (subaddressing_mode -> identifier -> identifier -> 'a1) -> (identifier ->
5554 'a1) -> ((subaddressing_mode, (subaddressing_mode, word_side) Types.prod)
5555 Types.sum -> identifier -> BitVector.word -> 'a1) -> pseudo_instruction
5557 let rec pseudo_instruction_rect_Type0 h_Instruction h_Comment h_Cost h_Jmp h_Jnz h_Call h_Mov = function
5558 | Instruction x_2170 -> h_Instruction x_2170
5559 | Comment x_2171 -> h_Comment x_2171
5560 | Cost x_2172 -> h_Cost x_2172
5561 | Jmp x_2173 -> h_Jmp x_2173
5562 | Jnz (x_2176, x_2175, x_2174) -> h_Jnz x_2176 x_2175 x_2174
5563 | Call x_2177 -> h_Call x_2177
5564 | Mov (x_2180, x_2179, x_2178) -> h_Mov x_2180 x_2179 x_2178
5566 (** val pseudo_instruction_inv_rect_Type4 :
5567 pseudo_instruction -> (identifier preinstruction -> __ -> 'a1) ->
5568 (String.string -> __ -> 'a1) -> (CostLabel.costlabel -> __ -> 'a1) ->
5569 (identifier -> __ -> 'a1) -> (subaddressing_mode -> identifier ->
5570 identifier -> __ -> 'a1) -> (identifier -> __ -> 'a1) ->
5571 ((subaddressing_mode, (subaddressing_mode, word_side) Types.prod)
5572 Types.sum -> identifier -> BitVector.word -> __ -> 'a1) -> 'a1 **)
5573 let pseudo_instruction_inv_rect_Type4 hterm h1 h2 h3 h4 h5 h6 h7 =
5574 let hcut = pseudo_instruction_rect_Type4 h1 h2 h3 h4 h5 h6 h7 hterm in
5577 (** val pseudo_instruction_inv_rect_Type3 :
5578 pseudo_instruction -> (identifier preinstruction -> __ -> 'a1) ->
5579 (String.string -> __ -> 'a1) -> (CostLabel.costlabel -> __ -> 'a1) ->
5580 (identifier -> __ -> 'a1) -> (subaddressing_mode -> identifier ->
5581 identifier -> __ -> 'a1) -> (identifier -> __ -> 'a1) ->
5582 ((subaddressing_mode, (subaddressing_mode, word_side) Types.prod)
5583 Types.sum -> identifier -> BitVector.word -> __ -> 'a1) -> 'a1 **)
5584 let pseudo_instruction_inv_rect_Type3 hterm h1 h2 h3 h4 h5 h6 h7 =
5585 let hcut = pseudo_instruction_rect_Type3 h1 h2 h3 h4 h5 h6 h7 hterm in
5588 (** val pseudo_instruction_inv_rect_Type2 :
5589 pseudo_instruction -> (identifier preinstruction -> __ -> 'a1) ->
5590 (String.string -> __ -> 'a1) -> (CostLabel.costlabel -> __ -> 'a1) ->
5591 (identifier -> __ -> 'a1) -> (subaddressing_mode -> identifier ->
5592 identifier -> __ -> 'a1) -> (identifier -> __ -> 'a1) ->
5593 ((subaddressing_mode, (subaddressing_mode, word_side) Types.prod)
5594 Types.sum -> identifier -> BitVector.word -> __ -> 'a1) -> 'a1 **)
5595 let pseudo_instruction_inv_rect_Type2 hterm h1 h2 h3 h4 h5 h6 h7 =
5596 let hcut = pseudo_instruction_rect_Type2 h1 h2 h3 h4 h5 h6 h7 hterm in
5599 (** val pseudo_instruction_inv_rect_Type1 :
5600 pseudo_instruction -> (identifier preinstruction -> __ -> 'a1) ->
5601 (String.string -> __ -> 'a1) -> (CostLabel.costlabel -> __ -> 'a1) ->
5602 (identifier -> __ -> 'a1) -> (subaddressing_mode -> identifier ->
5603 identifier -> __ -> 'a1) -> (identifier -> __ -> 'a1) ->
5604 ((subaddressing_mode, (subaddressing_mode, word_side) Types.prod)
5605 Types.sum -> identifier -> BitVector.word -> __ -> 'a1) -> 'a1 **)
5606 let pseudo_instruction_inv_rect_Type1 hterm h1 h2 h3 h4 h5 h6 h7 =
5607 let hcut = pseudo_instruction_rect_Type1 h1 h2 h3 h4 h5 h6 h7 hterm in
5610 (** val pseudo_instruction_inv_rect_Type0 :
5611 pseudo_instruction -> (identifier preinstruction -> __ -> 'a1) ->
5612 (String.string -> __ -> 'a1) -> (CostLabel.costlabel -> __ -> 'a1) ->
5613 (identifier -> __ -> 'a1) -> (subaddressing_mode -> identifier ->
5614 identifier -> __ -> 'a1) -> (identifier -> __ -> 'a1) ->
5615 ((subaddressing_mode, (subaddressing_mode, word_side) Types.prod)
5616 Types.sum -> identifier -> BitVector.word -> __ -> 'a1) -> 'a1 **)
5617 let pseudo_instruction_inv_rect_Type0 hterm h1 h2 h3 h4 h5 h6 h7 =
5618 let hcut = pseudo_instruction_rect_Type0 h1 h2 h3 h4 h5 h6 h7 hterm in
5621 (** val pseudo_instruction_discr :
5622 pseudo_instruction -> pseudo_instruction -> __ **)
5623 let pseudo_instruction_discr x y =
5624 Logic.eq_rect_Type2 x
5626 | Instruction a0 -> Obj.magic (fun _ dH -> dH __)
5627 | Comment a0 -> Obj.magic (fun _ dH -> dH __)
5628 | Cost a0 -> Obj.magic (fun _ dH -> dH __)
5629 | Jmp a0 -> Obj.magic (fun _ dH -> dH __)
5630 | Jnz (a0, a1, a2) -> Obj.magic (fun _ dH -> dH __ __ __)
5631 | Call a0 -> Obj.magic (fun _ dH -> dH __)
5632 | Mov (a0, a1, a2) -> Obj.magic (fun _ dH -> dH __ __ __)) y
5634 (** val pseudo_instruction_jmdiscr :
5635 pseudo_instruction -> pseudo_instruction -> __ **)
5636 let pseudo_instruction_jmdiscr x y =
5637 Logic.eq_rect_Type2 x
5639 | Instruction a0 -> Obj.magic (fun _ dH -> dH __)
5640 | Comment a0 -> Obj.magic (fun _ dH -> dH __)
5641 | Cost a0 -> Obj.magic (fun _ dH -> dH __)
5642 | Jmp a0 -> Obj.magic (fun _ dH -> dH __)
5643 | Jnz (a0, a1, a2) -> Obj.magic (fun _ dH -> dH __ __ __)
5644 | Call a0 -> Obj.magic (fun _ dH -> dH __)
5645 | Mov (a0, a1, a2) -> Obj.magic (fun _ dH -> dH __ __ __)) y
5647 type labelled_instruction = pseudo_instruction LabelledObjects.labelled_obj
5649 type assembly_program = instruction List.list
5651 (** val fetch_pseudo_instruction :
5652 labelled_instruction List.list -> BitVector.word -> (pseudo_instruction,
5653 BitVector.word) Types.prod **)
5654 let fetch_pseudo_instruction code_mem pc =
5655 let { Types.fst = lbl; Types.snd = instr } =
5657 (Arithmetic.nat_of_bitvector (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
5658 (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
5659 Nat.O)))))))))))))))) pc) code_mem
5662 Arithmetic.add (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
5663 (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
5664 Nat.O)))))))))))))))) pc
5665 (Arithmetic.bitvector_of_nat (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
5666 (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
5667 Nat.O)))))))))))))))) (Nat.S Nat.O))
5669 { Types.fst = instr; Types.snd = new_pc }
5671 (** val is_jump' : identifier preinstruction -> Bool.bool **)
5672 let is_jump' = function
5673 | ADD (x0, x1) -> Bool.False
5674 | ADDC (x0, x1) -> Bool.False
5675 | SUBB (x0, x1) -> Bool.False
5676 | INC x0 -> Bool.False
5677 | DEC x0 -> Bool.False
5678 | MUL (x0, x1) -> Bool.False
5679 | DIV (x0, x1) -> Bool.False
5680 | DA x0 -> Bool.False
5681 | JC x0 -> Bool.True
5682 | JNC x0 -> Bool.True
5683 | JB (x0, x1) -> Bool.True
5684 | JNB (x0, x1) -> Bool.True
5685 | JBC (x0, x1) -> Bool.True
5686 | JZ x0 -> Bool.True
5687 | JNZ x0 -> Bool.True
5688 | CJNE (x0, x1) -> Bool.True
5689 | DJNZ (x0, x1) -> Bool.True
5690 | ANL x0 -> Bool.False
5691 | ORL x0 -> Bool.False
5692 | XRL x0 -> Bool.False
5693 | CLR x0 -> Bool.False
5694 | CPL x0 -> Bool.False
5695 | RL x0 -> Bool.False
5696 | RLC x0 -> Bool.False
5697 | RR x0 -> Bool.False
5698 | RRC x0 -> Bool.False
5699 | SWAP x0 -> Bool.False
5700 | MOV x0 -> Bool.False
5701 | MOVX x0 -> Bool.False
5702 | SETB x0 -> Bool.False
5703 | PUSH x0 -> Bool.False
5704 | POP x0 -> Bool.False
5705 | XCH (x0, x1) -> Bool.False
5706 | XCHD (x0, x1) -> Bool.False
5708 | RETI -> Bool.False
5710 | JMP x0 -> Bool.False
5712 (** val is_relative_jump : pseudo_instruction -> Bool.bool **)
5713 let is_relative_jump = function
5714 | Instruction i -> is_jump' i
5715 | Comment x -> Bool.False
5716 | Cost x -> Bool.False
5717 | Jmp x -> Bool.False
5718 | Jnz (x, x0, x1) -> Bool.False
5719 | Call x -> Bool.False
5720 | Mov (x, x0, x1) -> Bool.False
5722 (** val is_jump : pseudo_instruction -> Bool.bool **)
5723 let is_jump = function
5724 | Instruction i -> is_jump' i
5725 | Comment x -> Bool.False
5726 | Cost x -> Bool.False
5727 | Jmp x -> Bool.True
5728 | Jnz (x, x0, x1) -> Bool.False
5729 | Call x -> Bool.True
5730 | Mov (x, x0, x1) -> Bool.False
5732 (** val is_call : pseudo_instruction -> Bool.bool **)
5733 let is_call = function
5734 | Instruction x -> Bool.False
5735 | Comment x -> Bool.False
5736 | Cost x -> Bool.False
5737 | Jmp x -> Bool.False
5738 | Jnz (x, x0, x1) -> Bool.False
5739 | Call x -> Bool.True
5740 | Mov (x, x0, x1) -> Bool.False
5742 (** val asm_cost_label :
5743 labelled_instruction List.list -> BitVector.word Types.sig0 ->
5744 CostLabel.costlabel Types.option **)
5745 let asm_cost_label mem w_prf =
5746 match (fetch_pseudo_instruction mem (Types.pi1 w_prf)).Types.fst with
5747 | Instruction x -> Types.None
5748 | Comment x -> Types.None
5749 | Cost c -> Types.Some c
5750 | Jmp x -> Types.None
5751 | Jnz (x, x0, x1) -> Types.None
5752 | Call x -> Types.None
5753 | Mov (x, x0, x1) -> Types.None
5755 (** val aDDRESS_WIDTH : Nat.nat **)
5757 Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
5758 (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S Nat.O)))))))))))))))
5760 (** val mAX_CODE_SIZE : Nat.nat **)
5762 Exp.exp (Nat.S (Nat.S Nat.O)) aDDRESS_WIDTH
5764 (** val code_size_opt : labelled_instruction List.list -> __ Types.option **)
5765 let code_size_opt code =
5766 Extranat.nat_bound_opt mAX_CODE_SIZE (Nat.S (List.length code))
5768 type pseudo_assembly_program = { preamble : (identifier, BitVector.word)
5769 Types.prod List.list;
5770 code : labelled_instruction List.list;
5771 renamed_symbols : (identifier, AST.ident)
5772 Types.prod List.list;
5773 final_label : identifier }
5775 (** val pseudo_assembly_program_rect_Type4 :
5776 ((identifier, BitVector.word) Types.prod List.list ->
5777 labelled_instruction List.list -> __ -> (identifier, AST.ident)
5778 Types.prod List.list -> identifier -> __ -> __ -> 'a1) ->
5779 pseudo_assembly_program -> 'a1 **)
5780 let rec pseudo_assembly_program_rect_Type4 h_mk_pseudo_assembly_program x_2304 =
5781 let { preamble = preamble0; code = code0; renamed_symbols =
5782 renamed_symbols0; final_label = final_label0 } = x_2304
5784 h_mk_pseudo_assembly_program preamble0 code0 __ renamed_symbols0
5787 (** val pseudo_assembly_program_rect_Type5 :
5788 ((identifier, BitVector.word) Types.prod List.list ->
5789 labelled_instruction List.list -> __ -> (identifier, AST.ident)
5790 Types.prod List.list -> identifier -> __ -> __ -> 'a1) ->
5791 pseudo_assembly_program -> 'a1 **)
5792 let rec pseudo_assembly_program_rect_Type5 h_mk_pseudo_assembly_program x_2306 =
5793 let { preamble = preamble0; code = code0; renamed_symbols =
5794 renamed_symbols0; final_label = final_label0 } = x_2306
5796 h_mk_pseudo_assembly_program preamble0 code0 __ renamed_symbols0
5799 (** val pseudo_assembly_program_rect_Type3 :
5800 ((identifier, BitVector.word) Types.prod List.list ->
5801 labelled_instruction List.list -> __ -> (identifier, AST.ident)
5802 Types.prod List.list -> identifier -> __ -> __ -> 'a1) ->
5803 pseudo_assembly_program -> 'a1 **)
5804 let rec pseudo_assembly_program_rect_Type3 h_mk_pseudo_assembly_program x_2308 =
5805 let { preamble = preamble0; code = code0; renamed_symbols =
5806 renamed_symbols0; final_label = final_label0 } = x_2308
5808 h_mk_pseudo_assembly_program preamble0 code0 __ renamed_symbols0
5811 (** val pseudo_assembly_program_rect_Type2 :
5812 ((identifier, BitVector.word) Types.prod List.list ->
5813 labelled_instruction List.list -> __ -> (identifier, AST.ident)
5814 Types.prod List.list -> identifier -> __ -> __ -> 'a1) ->
5815 pseudo_assembly_program -> 'a1 **)
5816 let rec pseudo_assembly_program_rect_Type2 h_mk_pseudo_assembly_program x_2310 =
5817 let { preamble = preamble0; code = code0; renamed_symbols =
5818 renamed_symbols0; final_label = final_label0 } = x_2310
5820 h_mk_pseudo_assembly_program preamble0 code0 __ renamed_symbols0
5823 (** val pseudo_assembly_program_rect_Type1 :
5824 ((identifier, BitVector.word) Types.prod List.list ->
5825 labelled_instruction List.list -> __ -> (identifier, AST.ident)
5826 Types.prod List.list -> identifier -> __ -> __ -> 'a1) ->
5827 pseudo_assembly_program -> 'a1 **)
5828 let rec pseudo_assembly_program_rect_Type1 h_mk_pseudo_assembly_program x_2312 =
5829 let { preamble = preamble0; code = code0; renamed_symbols =
5830 renamed_symbols0; final_label = final_label0 } = x_2312
5832 h_mk_pseudo_assembly_program preamble0 code0 __ renamed_symbols0
5835 (** val pseudo_assembly_program_rect_Type0 :
5836 ((identifier, BitVector.word) Types.prod List.list ->
5837 labelled_instruction List.list -> __ -> (identifier, AST.ident)
5838 Types.prod List.list -> identifier -> __ -> __ -> 'a1) ->
5839 pseudo_assembly_program -> 'a1 **)
5840 let rec pseudo_assembly_program_rect_Type0 h_mk_pseudo_assembly_program x_2314 =
5841 let { preamble = preamble0; code = code0; renamed_symbols =
5842 renamed_symbols0; final_label = final_label0 } = x_2314
5844 h_mk_pseudo_assembly_program preamble0 code0 __ renamed_symbols0
5848 pseudo_assembly_program -> (identifier, BitVector.word) Types.prod
5850 let rec preamble xxx =
5853 (** val code : pseudo_assembly_program -> labelled_instruction List.list **)
5857 (** val renamed_symbols :
5858 pseudo_assembly_program -> (identifier, AST.ident) Types.prod List.list **)
5859 let rec renamed_symbols xxx =
5862 (** val final_label : pseudo_assembly_program -> identifier **)
5863 let rec final_label xxx =
5866 (** val pseudo_assembly_program_inv_rect_Type4 :
5867 pseudo_assembly_program -> ((identifier, BitVector.word) Types.prod
5868 List.list -> labelled_instruction List.list -> __ -> (identifier,
5869 AST.ident) Types.prod List.list -> identifier -> __ -> __ -> __ -> 'a1)
5871 let pseudo_assembly_program_inv_rect_Type4 hterm h1 =
5872 let hcut = pseudo_assembly_program_rect_Type4 h1 hterm in hcut __
5874 (** val pseudo_assembly_program_inv_rect_Type3 :
5875 pseudo_assembly_program -> ((identifier, BitVector.word) Types.prod
5876 List.list -> labelled_instruction List.list -> __ -> (identifier,
5877 AST.ident) Types.prod List.list -> identifier -> __ -> __ -> __ -> 'a1)
5879 let pseudo_assembly_program_inv_rect_Type3 hterm h1 =
5880 let hcut = pseudo_assembly_program_rect_Type3 h1 hterm in hcut __
5882 (** val pseudo_assembly_program_inv_rect_Type2 :
5883 pseudo_assembly_program -> ((identifier, BitVector.word) Types.prod
5884 List.list -> labelled_instruction List.list -> __ -> (identifier,
5885 AST.ident) Types.prod List.list -> identifier -> __ -> __ -> __ -> 'a1)
5887 let pseudo_assembly_program_inv_rect_Type2 hterm h1 =
5888 let hcut = pseudo_assembly_program_rect_Type2 h1 hterm in hcut __
5890 (** val pseudo_assembly_program_inv_rect_Type1 :
5891 pseudo_assembly_program -> ((identifier, BitVector.word) Types.prod
5892 List.list -> labelled_instruction List.list -> __ -> (identifier,
5893 AST.ident) Types.prod List.list -> identifier -> __ -> __ -> __ -> 'a1)
5895 let pseudo_assembly_program_inv_rect_Type1 hterm h1 =
5896 let hcut = pseudo_assembly_program_rect_Type1 h1 hterm in hcut __
5898 (** val pseudo_assembly_program_inv_rect_Type0 :
5899 pseudo_assembly_program -> ((identifier, BitVector.word) Types.prod
5900 List.list -> labelled_instruction List.list -> __ -> (identifier,
5901 AST.ident) Types.prod List.list -> identifier -> __ -> __ -> __ -> 'a1)
5903 let pseudo_assembly_program_inv_rect_Type0 hterm h1 =
5904 let hcut = pseudo_assembly_program_rect_Type0 h1 hterm in hcut __
5906 (** val pseudo_assembly_program_jmdiscr :
5907 pseudo_assembly_program -> pseudo_assembly_program -> __ **)
5908 let pseudo_assembly_program_jmdiscr x y =
5909 Logic.eq_rect_Type2 x
5910 (let { preamble = a0; code = a1; renamed_symbols = a3; final_label =
5913 Obj.magic (fun _ dH -> dH __ __ __ __ __ __ __)) y
5915 type object_code = BitVector.byte List.list
5918 BitVector.byte BitVectorTrie.bitVectorTrie -> BitVector.word ->
5919 (BitVector.word, BitVector.byte) Types.prod **)
5922 (Arithmetic.add (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
5923 (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
5924 Nat.O)))))))))))))))) pc
5925 (Arithmetic.bitvector_of_nat (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
5926 (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
5927 Nat.O)))))))))))))))) (Nat.S Nat.O))); Types.snd =
5928 (BitVectorTrie.lookup (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
5929 (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
5930 Nat.O)))))))))))))))) pc pmem
5931 (BitVector.zero (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
5934 (** val load_code_memory0 :
5935 object_code -> BitVector.byte BitVectorTrie.bitVectorTrie Types.sig0 **)
5936 let load_code_memory0 program =
5938 (FoldStuff.foldl_strong program (fun prefix v tl _ i_mem ->
5939 (let { Types.fst = eta24568; Types.snd = mem } = Types.pi1 i_mem in
5941 (let { Types.fst = i; Types.snd = bvi } = eta24568 in
5942 (fun _ -> { Types.fst = { Types.fst = (Nat.S i); Types.snd =
5943 (Arithmetic.increment (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
5944 (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
5945 Nat.O)))))))))))))))) bvi) }; Types.snd =
5946 (BitVectorTrie.insert (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
5947 (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
5948 Nat.O)))))))))))))))) bvi v mem) })) __)) __) { Types.fst =
5949 { Types.fst = Nat.O; Types.snd =
5950 (BitVector.zero (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
5951 (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
5952 Nat.O))))))))))))))))) }; Types.snd = (BitVectorTrie.Stub (Nat.S
5953 (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S
5954 (Nat.S (Nat.S (Nat.S (Nat.S (Nat.S Nat.O))))))))))))))))) })).Types.snd
5956 (** val load_code_memory :
5957 object_code -> BitVector.byte BitVectorTrie.bitVectorTrie **)
5958 let load_code_memory program =
5959 Types.pi1 (load_code_memory0 program)
5961 type costlabel_map = CostLabel.costlabel BitVectorTrie.bitVectorTrie
5963 type symboltable_type = AST.ident BitVectorTrie.bitVectorTrie
5965 type labelled_object_code = { oc : object_code;
5966 cm : BitVector.byte BitVectorTrie.bitVectorTrie;
5967 costlabels : costlabel_map;
5968 symboltable : symboltable_type;
5969 final_pc : BitVector.word }
5971 (** val labelled_object_code_rect_Type4 :
5972 (object_code -> BitVector.byte BitVectorTrie.bitVectorTrie -> __ ->
5973 costlabel_map -> symboltable_type -> BitVector.word -> __ -> 'a1) ->
5974 labelled_object_code -> 'a1 **)
5975 let rec labelled_object_code_rect_Type4 h_mk_labelled_object_code x_2330 =
5976 let { oc = oc0; cm = cm0; costlabels = costlabels0; symboltable =
5977 symboltable0; final_pc = final_pc0 } = x_2330
5979 h_mk_labelled_object_code oc0 cm0 __ costlabels0 symboltable0 final_pc0 __
5981 (** val labelled_object_code_rect_Type5 :
5982 (object_code -> BitVector.byte BitVectorTrie.bitVectorTrie -> __ ->
5983 costlabel_map -> symboltable_type -> BitVector.word -> __ -> 'a1) ->
5984 labelled_object_code -> 'a1 **)
5985 let rec labelled_object_code_rect_Type5 h_mk_labelled_object_code x_2332 =
5986 let { oc = oc0; cm = cm0; costlabels = costlabels0; symboltable =
5987 symboltable0; final_pc = final_pc0 } = x_2332
5989 h_mk_labelled_object_code oc0 cm0 __ costlabels0 symboltable0 final_pc0 __
5991 (** val labelled_object_code_rect_Type3 :
5992 (object_code -> BitVector.byte BitVectorTrie.bitVectorTrie -> __ ->
5993 costlabel_map -> symboltable_type -> BitVector.word -> __ -> 'a1) ->
5994 labelled_object_code -> 'a1 **)
5995 let rec labelled_object_code_rect_Type3 h_mk_labelled_object_code x_2334 =
5996 let { oc = oc0; cm = cm0; costlabels = costlabels0; symboltable =
5997 symboltable0; final_pc = final_pc0 } = x_2334
5999 h_mk_labelled_object_code oc0 cm0 __ costlabels0 symboltable0 final_pc0 __
6001 (** val labelled_object_code_rect_Type2 :
6002 (object_code -> BitVector.byte BitVectorTrie.bitVectorTrie -> __ ->
6003 costlabel_map -> symboltable_type -> BitVector.word -> __ -> 'a1) ->
6004 labelled_object_code -> 'a1 **)
6005 let rec labelled_object_code_rect_Type2 h_mk_labelled_object_code x_2336 =
6006 let { oc = oc0; cm = cm0; costlabels = costlabels0; symboltable =
6007 symboltable0; final_pc = final_pc0 } = x_2336
6009 h_mk_labelled_object_code oc0 cm0 __ costlabels0 symboltable0 final_pc0 __
6011 (** val labelled_object_code_rect_Type1 :
6012 (object_code -> BitVector.byte BitVectorTrie.bitVectorTrie -> __ ->
6013 costlabel_map -> symboltable_type -> BitVector.word -> __ -> 'a1) ->
6014 labelled_object_code -> 'a1 **)
6015 let rec labelled_object_code_rect_Type1 h_mk_labelled_object_code x_2338 =
6016 let { oc = oc0; cm = cm0; costlabels = costlabels0; symboltable =
6017 symboltable0; final_pc = final_pc0 } = x_2338
6019 h_mk_labelled_object_code oc0 cm0 __ costlabels0 symboltable0 final_pc0 __
6021 (** val labelled_object_code_rect_Type0 :
6022 (object_code -> BitVector.byte BitVectorTrie.bitVectorTrie -> __ ->
6023 costlabel_map -> symboltable_type -> BitVector.word -> __ -> 'a1) ->
6024 labelled_object_code -> 'a1 **)
6025 let rec labelled_object_code_rect_Type0 h_mk_labelled_object_code x_2340 =
6026 let { oc = oc0; cm = cm0; costlabels = costlabels0; symboltable =
6027 symboltable0; final_pc = final_pc0 } = x_2340
6029 h_mk_labelled_object_code oc0 cm0 __ costlabels0 symboltable0 final_pc0 __
6031 (** val oc : labelled_object_code -> object_code **)
6036 labelled_object_code -> BitVector.byte BitVectorTrie.bitVectorTrie **)
6040 (** val costlabels : labelled_object_code -> costlabel_map **)
6041 let rec costlabels xxx =
6044 (** val symboltable : labelled_object_code -> symboltable_type **)
6045 let rec symboltable xxx =
6048 (** val final_pc : labelled_object_code -> BitVector.word **)
6049 let rec final_pc xxx =
6052 (** val labelled_object_code_inv_rect_Type4 :
6053 labelled_object_code -> (object_code -> BitVector.byte
6054 BitVectorTrie.bitVectorTrie -> __ -> costlabel_map -> symboltable_type ->
6055 BitVector.word -> __ -> __ -> 'a1) -> 'a1 **)
6056 let labelled_object_code_inv_rect_Type4 hterm h1 =
6057 let hcut = labelled_object_code_rect_Type4 h1 hterm in hcut __
6059 (** val labelled_object_code_inv_rect_Type3 :
6060 labelled_object_code -> (object_code -> BitVector.byte
6061 BitVectorTrie.bitVectorTrie -> __ -> costlabel_map -> symboltable_type ->
6062 BitVector.word -> __ -> __ -> 'a1) -> 'a1 **)
6063 let labelled_object_code_inv_rect_Type3 hterm h1 =
6064 let hcut = labelled_object_code_rect_Type3 h1 hterm in hcut __
6066 (** val labelled_object_code_inv_rect_Type2 :
6067 labelled_object_code -> (object_code -> BitVector.byte
6068 BitVectorTrie.bitVectorTrie -> __ -> costlabel_map -> symboltable_type ->
6069 BitVector.word -> __ -> __ -> 'a1) -> 'a1 **)
6070 let labelled_object_code_inv_rect_Type2 hterm h1 =
6071 let hcut = labelled_object_code_rect_Type2 h1 hterm in hcut __
6073 (** val labelled_object_code_inv_rect_Type1 :
6074 labelled_object_code -> (object_code -> BitVector.byte
6075 BitVectorTrie.bitVectorTrie -> __ -> costlabel_map -> symboltable_type ->
6076 BitVector.word -> __ -> __ -> 'a1) -> 'a1 **)
6077 let labelled_object_code_inv_rect_Type1 hterm h1 =
6078 let hcut = labelled_object_code_rect_Type1 h1 hterm in hcut __
6080 (** val labelled_object_code_inv_rect_Type0 :
6081 labelled_object_code -> (object_code -> BitVector.byte
6082 BitVectorTrie.bitVectorTrie -> __ -> costlabel_map -> symboltable_type ->
6083 BitVector.word -> __ -> __ -> 'a1) -> 'a1 **)
6084 let labelled_object_code_inv_rect_Type0 hterm h1 =
6085 let hcut = labelled_object_code_rect_Type0 h1 hterm in hcut __
6087 (** val labelled_object_code_jmdiscr :
6088 labelled_object_code -> labelled_object_code -> __ **)
6089 let labelled_object_code_jmdiscr x y =
6090 Logic.eq_rect_Type2 x
6091 (let { oc = a0; cm = a1; costlabels = a3; symboltable = a4; final_pc =
6094 Obj.magic (fun _ dH -> dH __ __ __ __ __ __ __)) y