1 (**************************************************************************)
4 (* ||A|| A project by Andrea Asperti *)
6 (* ||I|| Developers: *)
7 (* ||T|| The HELM team. *)
8 (* ||A|| http://helm.cs.unibo.it *)
10 (* \ / This file is distributed under the terms of the *)
11 (* v GNU General Public License Version 2 *)
13 (**************************************************************************)
15 (* ********************************************************************** *)
16 (* Progetto FreeScale *)
18 (* Sviluppato da: Ing. Cosimo Oliboni, oliboni@cs.unibo.it *)
19 (* Ultima modifica: 05/08/2009 *)
21 (* ********************************************************************** *)
23 include "freescale_tests/micro_tests_tools.ma".
24 include "freescale/multivm.ma".
25 include "freescale/status_lemmas.ma".
27 (* ****************************************** *)
28 (* MICRO TEST DI CORRETTEZZA DELLE ISTRUZIONI *)
29 (* ****************************************** *)
35 ndefinition mTest_RS08_SRT_source ≝ let m ≝ RS08 in source_to_byte8 m (
36 (* testa la logica RS08 PS le modalita' SRT *)
37 (* NB: il meccanismo utilizzato e' quello complesso dell'RS08
38 fare riferimento alle spiegazioni in STATUS/LOAD_WRITE *)
39 (* X=0x1F PS=0xFE Z=1 *)
40 (* [0x3800] 3clk *) (compile m ? LDA (maSRT t1F) I) @ (* A<-PS *)
41 (* [0x3801] 2clk *) (compile m ? SUB (maIMM1 〈xF,xE〉) I) @ (* risulta 0 *)
42 (* [0x3803] 3clk *) (compile m ? BEQ (maIMM1 〈x0,x1〉) I) @ (* salta *)
43 (* [0x3805] 1clk *) (compile m ? NOP maINH I) @
45 (* [0x3806] 3clk *) (compile m ? LDA (maSRT t0E) I) @ (* A<-PS *)
46 (* [0x3807] 2clk *) (compile m ? SUB (maIMM1 〈xF,xE〉) I) @ (* risulta 0 *)
47 (* [0x3809] 3clk *) (compile m ? BEQ (maIMM1 〈x0,x1〉) I) @ (* salta *)
48 (* [0x380B] 1clk *) (compile m ? NOP maINH I) @
50 (* [0x380C] 3clk *) (compile m ? LDA (maDIR1 〈xC,x3〉) I) @ (* A<-[0x00C3]=[0x3F83]=0x83 *)
51 (* [0x380E] 2clk *) (compile m ? SUB (maIMM1 〈x8,x3〉) I) @ (* risulta 0 *)
52 (* [0x3810] 3clk *) (compile m ? BEQ (maIMM1 〈x0,x1〉) I) @ (* salta *)
53 (* [0x3812] 1clk *) (compile m ? NOP maINH I)
54 (* [0x3813] si puo' quindi enunciare che dopo 24 clk
58 (* creazione del processore+caricamento+impostazione registri *)
59 ndefinition mTest_RS08_SRT_status ≝
61 setweak_x_map RS08 t (* X<-0x1F *)
62 (setweak_ps_map RS08 t (* PS<-0xFE *)
63 (set_z_flag RS08 t (* Z<-true *)
64 (set_pc_reg RS08 t (* PC<-mTest_RS08_prog *)
65 (start_of_mcu_version_RS08
67 (load_from_source_at t (* carica mTest_bytes in ROM:mTest_RS08_data *)
68 (load_from_source_at t (zero_memory t) (* carica source in ROM:mTest_RS08_prog *)
69 mTest_RS08_SRT_source mTest_RS08_prog)
70 mTest_bytes mTest_RS08_data)
71 (build_memory_type_of_mcu_version (FamilyRS08 MC9RS08KA2) t)
72 (mk_byte8 x0 x0) (mk_byte8 x0 x0) (* non deterministici tutti a 0 *)
73 false false false false false false (* non deterministici tutti a 0 *)
79 (* dimostrazione senza svolgimento degli stati, immediata *)
80 nlemma ok_mTest_RS08_SRT_full :
82 execute RS08 t (TickOK ? (mTest_RS08_SRT_status t)) nat24 =
83 TickOK ? (set_pc_reg RS08 t (mTest_RS08_SRT_status t) (* nuovo PC *)
84 (mk_word16 〈x3,x8〉 〈x1,x3〉)).