open Preamble

open Extra_bool

open Coqlib

open Values

open FrontEndVal

open GenMem

open FrontEndMem

open Globalenvs

open String

open Sets

open Listb

open LabelledObjects

open BitVectorTrie

open Graphs

open I8051

open Order

open Registers

open CostLabel

open Hide

open Proper

open PositiveMap

open Deqsets

open ErrorMessages

open PreIdentifiers

open Errors

open Extralib

open Lists

open Identifiers

open Integers

open AST

open Division

open Exp

open Arithmetic

open Setoids

open Monad

open Option

open Extranat

open Vector

open Div_and_mod

open Jmeq

open Russell

open List

open Util

open FoldStuff

open BitVector

open Types

open Bool

open Relations

open Nat

open Hints_declaration

open Core_notation

open Pts

open Logic

open Positive

open Z

open BitVectorZ

open Pointers

open ByteValues

open BackEndOps

open Joint

type rtl_seq =
| Rtl_stack_address of Registers.register * Registers.register

val rtl_seq_rect_Type4 :
  (Registers.register -> Registers.register -> 'a1) -> rtl_seq -> 'a1

val rtl_seq_rect_Type5 :
  (Registers.register -> Registers.register -> 'a1) -> rtl_seq -> 'a1

val rtl_seq_rect_Type3 :
  (Registers.register -> Registers.register -> 'a1) -> rtl_seq -> 'a1

val rtl_seq_rect_Type2 :
  (Registers.register -> Registers.register -> 'a1) -> rtl_seq -> 'a1

val rtl_seq_rect_Type1 :
  (Registers.register -> Registers.register -> 'a1) -> rtl_seq -> 'a1

val rtl_seq_rect_Type0 :
  (Registers.register -> Registers.register -> 'a1) -> rtl_seq -> 'a1

val rtl_seq_inv_rect_Type4 :
  rtl_seq -> (Registers.register -> Registers.register -> __ -> 'a1) -> 'a1

val rtl_seq_inv_rect_Type3 :
  rtl_seq -> (Registers.register -> Registers.register -> __ -> 'a1) -> 'a1

val rtl_seq_inv_rect_Type2 :
  rtl_seq -> (Registers.register -> Registers.register -> __ -> 'a1) -> 'a1

val rtl_seq_inv_rect_Type1 :
  rtl_seq -> (Registers.register -> Registers.register -> __ -> 'a1) -> 'a1

val rtl_seq_inv_rect_Type0 :
  rtl_seq -> (Registers.register -> Registers.register -> __ -> 'a1) -> 'a1

val rtl_seq_discr : rtl_seq -> rtl_seq -> __

val rtl_seq_jmdiscr : rtl_seq -> rtl_seq -> __

val rTL_uns : Joint.unserialized_params

val rTL_functs : Joint.get_pseudo_reg_functs

val rTL : Joint.graph_params

type rtl_program = Joint.joint_program

val dpi1__o__reg_to_rtl_snd_argument__o__inject :
  (Registers.register, 'a1) Types.dPair -> Joint.psd_argument Types.sig0

val eject__o__reg_to_rtl_snd_argument__o__inject :
  Registers.register Types.sig0 -> Joint.psd_argument Types.sig0

val reg_to_rtl_snd_argument__o__inject :
  Registers.register -> Joint.psd_argument Types.sig0

val dpi1__o__reg_to_rtl_snd_argument :
  (Registers.register, 'a1) Types.dPair -> Joint.psd_argument

val eject__o__reg_to_rtl_snd_argument :
  Registers.register Types.sig0 -> Joint.psd_argument

val dpi1__o__byte_to_rtl_snd_argument__o__inject :
  (BitVector.byte, 'a1) Types.dPair -> Joint.psd_argument Types.sig0

val eject__o__byte_to_rtl_snd_argument__o__inject :
  BitVector.byte Types.sig0 -> Joint.psd_argument Types.sig0

val byte_to_rtl_snd_argument__o__inject :
  BitVector.byte -> Joint.psd_argument Types.sig0

val dpi1__o__byte_to_rtl_snd_argument :
  (BitVector.byte, 'a1) Types.dPair -> Joint.psd_argument

val eject__o__byte_to_rtl_snd_argument :
  BitVector.byte Types.sig0 -> Joint.psd_argument

val rTL_premain : rtl_program -> Joint.joint_closed_internal_function