include Arch.S

type opaccs =
  | Mul
  | DivuModu

type op1 =
  | Cmpl
  | Inc

type op2 =
  | Add
  | Addc
  | Sub
  | And
  | Or
  | Xor

val print_opaccs : opaccs -> string
val print_op1 : op1 -> string
val print_op2 : op2 -> string

module Eval (Val : Value.S) : sig
  val opaccs : opaccs -> Val.t -> Val.t ->
               (Val.t (* first result (ACC) *) *
	        Val.t (* second result (BACC) *))
  val op1    : op1 -> Val.t -> Val.t
  val op2    : Val.t (* carry *) -> op2 -> Val.t -> Val.t ->
               (Val.t (* returned value *) * Val.t (* new carry value *))
end

(* Not supported: signed division, signed modulo, shift operations. *)

type register
val compare_reg : register -> register -> int
val eq_reg      : register -> register -> bool

module RegisterSet : Set.S with type elt = register
module RegisterMap : Map.S with type key = register

val a : register
val b : register
val dpl : register
val dph : register
val spl : register
val sph : register
val st0 : register
val st1 : register
val st2 : register
val st3 : register
val sts : register list
val rets : register list
val sst : register
val carry : register (* only used for the liveness analysis *)

val spl_addr : int
val spl_init : int
val sph_addr : int
val sph_init : int
val isp_addr : int
val isp_init : int

val registers : RegisterSet.t
val parameters : register list
val callee_saved : RegisterSet.t
val caller_saved : RegisterSet.t
val allocatable : RegisterSet.t
val forbidden : RegisterSet.t

val print_register : register -> string

val reg_addr : register -> [> ASM.direct]

val ext_ram_size : int
val int_ram_size : int