--- /dev/null
+(**************************************************************************)
+(* ___ *)
+(* ||M|| *)
+(* ||A|| A project by Andrea Asperti *)
+(* ||T|| *)
+(* ||I|| Developers: *)
+(* ||T|| The HELM team. *)
+(* ||A|| http://helm.cs.unibo.it *)
+(* \ / *)
+(* \ / This file is distributed under the terms of the *)
+(* v GNU General Public License Version 2 *)
+(* *)
+(**************************************************************************)
+
+(* ********************************************************************** *)
+(* Progetto FreeScale *)
+(* *)
+(* Sviluppato da: Ing. Cosimo Oliboni, oliboni@cs.unibo.it *)
+(* Ultima modifica: 05/08/2009 *)
+(* *)
+(* ********************************************************************** *)
+
+include "freescale_tests/micro_tests_tools.ma".
+include "freescale/multivm.ma".
+include "freescale/status_lemmas.ma".
+
+(* ****************************************** *)
+(* MICRO TEST DI CORRETTEZZA DELLE ISTRUZIONI *)
+(* ****************************************** *)
+
+(* *********** *)
+(* RS08 PS,SRT *)
+(* *********** *)
+
+ndefinition mTest_RS08_SRT_source ≝ let m ≝ RS08 in source_to_byte8 m (
+(* testa la logica RS08 PS le modalita' SRT *)
+(* NB: il meccanismo utilizzato e' quello complesso dell'RS08
+ fare riferimento alle spiegazioni in STATUS/LOAD_WRITE *)
+(* X=0x1F PS=0xFE Z=1 *)
+(* [0x3800] 3clk *) (compile m ? LDA (maSRT t1F) I) @ (* A<-PS *)
+(* [0x3801] 2clk *) (compile m ? SUB (maIMM1 〈xF,xE〉) I) @ (* risulta 0 *)
+(* [0x3803] 3clk *) (compile m ? BEQ (maIMM1 〈x0,x1〉) I) @ (* salta *)
+(* [0x3805] 1clk *) (compile m ? NOP maINH I) @
+
+(* [0x3806] 3clk *) (compile m ? LDA (maSRT t0E) I) @ (* A<-PS *)
+(* [0x3807] 2clk *) (compile m ? SUB (maIMM1 〈xF,xE〉) I) @ (* risulta 0 *)
+(* [0x3809] 3clk *) (compile m ? BEQ (maIMM1 〈x0,x1〉) I) @ (* salta *)
+(* [0x380B] 1clk *) (compile m ? NOP maINH I) @
+
+(* [0x380C] 3clk *) (compile m ? LDA (maDIR1 〈xC,x3〉) I) @ (* A<-[0x00C3]=[0x3F83]=0x83 *)
+(* [0x380E] 2clk *) (compile m ? SUB (maIMM1 〈x8,x3〉) I) @ (* risulta 0 *)
+(* [0x3810] 3clk *) (compile m ? BEQ (maIMM1 〈x0,x1〉) I) @ (* salta *)
+(* [0x3812] 1clk *) (compile m ? NOP maINH I)
+(* [0x3813] si puo' quindi enunciare che dopo 24 clk
+ PC<-0x3813 *)
+).
+
+(* creazione del processore+caricamento+impostazione registri *)
+ndefinition mTest_RS08_SRT_status ≝
+λt:memory_impl.
+ setweak_x_map RS08 t (* X<-0x1F *)
+ (setweak_ps_map RS08 t (* PS<-0xFE *)
+ (set_z_flag RS08 t (* Z<-true *)
+ (set_pc_reg RS08 t (* PC<-mTest_RS08_prog *)
+ (start_of_mcu_version_RS08
+ MC9RS08KA2 t
+ (load_from_source_at t (* carica mTest_bytes in ROM:mTest_RS08_data *)
+ (load_from_source_at t (zero_memory t) (* carica source in ROM:mTest_RS08_prog *)
+ mTest_RS08_SRT_source mTest_RS08_prog)
+ mTest_bytes mTest_RS08_data)
+ (build_memory_type_of_mcu_version (FamilyRS08 MC9RS08KA2) t)
+ (mk_byte8 x0 x0) (mk_byte8 x0 x0) (* non deterministici tutti a 0 *)
+ false false false false false false (* non deterministici tutti a 0 *)
+ ) mTest_RS08_prog)
+ true)
+ (mk_byte8 xF xE))
+ (mk_byte8 x1 xF).
+
+(* dimostrazione senza svolgimento degli stati, immediata *)
+nlemma ok_mTest_RS08_SRT_full :
+ ∀t:memory_impl.
+ execute RS08 t (TickOK ? (mTest_RS08_SRT_status t)) nat24 =
+ TickOK ? (set_pc_reg RS08 t (mTest_RS08_SRT_status t) (* nuovo PC *)
+ (mk_word16 〈x3,x8〉 〈x1,x3〉)).
+ #t; nelim t;
+ napply refl_eq.
+nqed.